Simplified VHDL Coding of Modified Non-Restoring Square Root Calculator

2012 ◽  
Vol 1 (1) ◽  
pp. 37 ◽  
Author(s):  
Tole Sutikno ◽  
Aiman Zakwan Jidin ◽  
Auzani Jidin ◽  
Nik Rumzi Nik Idris
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Hardware Implementation ◽  
Digital Signal ◽  
Square Root ◽  
Main Principle ◽  
Hardware Resource ◽  
Root Operation ◽  
Hardware Designs

Square root calculation is one of the most useful and vital operation in digital signal processing which in recent generations of processors, the operation is performed by the hardware. The hardware implementation of the square root operation can be achieved by different means, but it is very dependent on programmer's sense and ability to write efficient hardware designs. This paper offers universal and shortest VHDL coding of modified non-restoring square root calculator. The main principle of the method is similar with conventional non-restoring algorithm, but it only uses subtract operation and append 01, while add operation and append 11 is not used. The strategy has conducted to implement successfully in FPGA hardware, and offer an efficient in hardware resource, and it is superior.

scholarly journals Performing Text – To – Speech based Hidden Markov Model on Digital Signal Processing platform

2014 ◽  
Vol 17 (1) ◽  
pp. 32-38
Author(s):  
Nhat Truong Minh Vu ◽  
Binh Hieu Nguyen ◽  
Nhat Minh Pham ◽  
Thuan Huu Huynh ◽  
Tu Trong Bui ◽  
...  
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Markov Model ◽  
Hidden Markov Model ◽  
Hardware Implementation ◽  
Hidden Markov ◽  
Digital Signal ◽  
Text To Speech ◽  
Processing Platform

Text To Speech (TTS) using Hidden Markov Model (HMM) has become popular in recent years. However, because most of such systems were implemented on personal computers (PCs), it is difficult to offer these systems to real applications. In this paper, we present a hardware implementation of TTS based on DSP architecture, which is applicable for real applications. By optimizing hardware architecture, the quality of the DSP-based synthesized speech is nearly identical to that synthesized on PCs.

scholarly journals An Efficient Reverse Converter for the Four Non Coprime Moduli Set {2n,2n-1,2n-2,2n-3}

2021 ◽  
Vol 10 (1) ◽  
pp. 29-34
Author(s):  
Valentine Aveyom ◽  
Abdul Barik Alhassan ◽  
Paula Aninyie Wumnaya
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Hardware Implementation ◽  
Dynamic Range ◽  
State Of The Art ◽  
Common Factor ◽  
Digital Signal ◽  
Reverse Converter ◽  
Dsp Applications

In this paper, residue to binary conversion is presented for the four moduli setsharing a common factor. A new and efficient converter for the moduli set using multipliers, carry saves and modular adders is proposed based on a cyclic jump approach. A theoretical hardware implementation and comparison with a state-of- the- art scheme showed that the proposed scheme performed better. The 4- moduli set selected provides a larger dynamic range which is needed for Digital Signal Processing (DSP) applications [7].

scholarly journals An efficient hardware logarithm generator with modified quasi-symmetrical approach for digital signal processing

2020 ◽  
Vol 10 (5) ◽  
pp. 4671
Author(s):  
Minh-Hong Nguyen
Keyword(s):  
Signal Processing ◽  
Error Analysis ◽  
Digital Signal Processing ◽  
Real Time ◽  
High Speed ◽  
Hardware Implementation ◽  
Approximation Error ◽  
Digital Signal ◽  
Traditional Methods ◽  
Low Area

This paper presents a low-error, low-area FPGA-based hardware logarithm generator for digital signal processing systems which require high-speed, real time logarithm operations. The proposed logarithm generator employs the modified quasi-symmetrical approach for an efficient hardware implementation. The error analysis and implementation results are also presented and discussed. The achieved results show that the proposed approach can reduce the approximation error and hardware area compared with traditional methods.

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