scholarly journals An Efficient Reverse Converter for the Four Non Coprime Moduli Set {2n,2n-1,2n-2,2n-3}

2021 ◽  
Vol 10 (1) ◽  
pp. 29-34
Author(s):  
Valentine Aveyom ◽  
Abdul Barik Alhassan ◽  
Paula Aninyie Wumnaya
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Hardware Implementation ◽  
Dynamic Range ◽  
State Of The Art ◽  
Common Factor ◽  
Digital Signal ◽  
Reverse Converter ◽  
Dsp Applications

In this paper, residue to binary conversion is presented for the four moduli setsharing a common factor. A new and efficient converter for the moduli set using multipliers, carry saves and modular adders is proposed based on a cyclic jump approach. A theoretical hardware implementation and comparison with a state-of- the- art scheme showed that the proposed scheme performed better. The 4- moduli set selected provides a larger dynamic range which is needed for Digital Signal Processing (DSP) applications [7].

Approximate Compressor-Based Multiplier Design Methodology for Error-Resilient Digital Signal Processing

2020 ◽  
Vol 29 (14) ◽  
pp. 2050233
Author(s):  
Zhixi Yang ◽  
Xianbin Li ◽  
Jun Yang
Keyword(s):  
Image Processing ◽  
Signal Processing ◽  
Digital Signal Processing ◽  
Resource Utilization ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Electrical Performance ◽  
Approximate Computing ◽  
Dsp Applications

As many digital signal processing (DSP) applications such as digital filtering are inherently error-tolerant, approximate computing has attracted significant attention. A multiplier is the fundamental component for DSP applications and takes up the most part of the resource utilization, namely power and area. A multiplier consists of partial product arrays (PPAs) and compressors are often used to reduce partial products (PPs) to generate the final product. Approximate computing has been studied as an innovative paradigm for reducing resource utilization for the DSP systems. In this paper, a 4:2 approximate compressor-based multiplier is studied. Approximate 4:2 compressors are designed with a practical design criterion, and an approximate multiplier that uses both truncation and the proposed compressors for PP reduction is subsequently designed. Different levels of truncation and approximate compression combination are studied for accuracy and electrical performance. A practical selection algorithm is then leveraged to identify the optimal combinations for multiplier designs with better performance in terms of both accuracy and electrical performance measurements. Two real case studies are performed, i.e., image processing and a finite impulse response (FIR) filter. The design proposed in this paper has achieved up to 16.96% and 20.81% savings on power and area with an average signal-to-noise ratio (SNR) larger than 25[Formula: see text]dB for image processing; similarly, with a decrease of 0.3[Formula: see text]dB in the output SNR, 12.22% and 30.05% savings on power and area have been achieved for an FIR filter compared to conventional multiplier designs.

Simplified VHDL Coding of Modified Non-Restoring Square Root Calculator

2012 ◽  
Vol 1 (1) ◽  
pp. 37 ◽  
Author(s):  
Tole Sutikno ◽  
Aiman Zakwan Jidin ◽  
Auzani Jidin ◽  
Nik Rumzi Nik Idris
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Hardware Implementation ◽  
Digital Signal ◽  
Square Root ◽  
Main Principle ◽  
Hardware Resource ◽  
Root Operation ◽  
Hardware Designs

Square root calculation is one of the most useful and vital operation in digital signal processing which in recent generations of processors, the operation is performed by the hardware. The hardware implementation of the square root operation can be achieved by different means, but it is very dependent on programmer's sense and ability to write efficient hardware designs. This paper offers universal and shortest VHDL coding of modified non-restoring square root calculator. The main principle of the method is similar with conventional non-restoring algorithm, but it only uses subtract operation and append 01, while add operation and append 11 is not used. The strategy has conducted to implement successfully in FPGA hardware, and offer an efficient in hardware resource, and it is superior.

High-dynamic-range fiber gyro with all-digital signal processing

1991 ◽  
Author(s):  
Herve C. Lefevre ◽  
Philippe Martin ◽  
J. Morisse ◽  
Pascal Simonpietri ◽  
P. Vivenot ◽  
...  
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Dynamic Range ◽  
Digital Signal ◽  
High Dynamic Range ◽  
High Dynamic
Sign in / Sign up

Export Citation Format

Share Document