Process Variability Aware Low Leakage Reliable Nano Scale Double-Gate-FinFET SRAM Cell Design Technique

Journal of Nanoelectronics and Optoelectronics ◽

10.1166/jno.2015.1843 ◽

2015 ◽

Vol 10 (6) ◽

pp. 810-817 ◽

Author(s):

Saurabh Khandelwal ◽

Vishal Gupta ◽

Balwinder Raj ◽

R. D. Gupta

Keyword(s):

Double Gate ◽

Cell Design ◽

Design Technique ◽

Process Variability ◽

Low Leakage ◽

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Variability aware low leakage reliable SRAM cell design technique

Microelectronics Reliability ◽

10.1016/j.microrel.2012.01.003 ◽

2012 ◽

Vol 52 (6) ◽

pp. 1247-1252 ◽

Author(s):

A. Islam ◽

Mohd. Hasan

Keyword(s):

Cell Design ◽

Design Technique ◽

Low Leakage ◽

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6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

Semiconductor Science and Technology ◽

10.1088/0268-1242/23/7/075049 ◽

2008 ◽

Vol 23 (7) ◽

pp. 075049 ◽

Author(s):

Rashmi ◽

Abhinav Kranti ◽

G Alastair Armstrong

Keyword(s):

Double Gate ◽

Cell Design ◽

Circuit Topology ◽

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A Novel SRAM Cell Design with a Body-Bias Controller Circuit for Low Leakage, High Speed and Improved Stability

Wireless Personal Communications ◽

10.1007/s11277-016-3788-5 ◽

2016 ◽

Vol 94 (4) ◽

pp. 3513-3529 ◽

Author(s):

Rohit Lorenzo ◽

Saurabh Chaudhury

Keyword(s):

Cell Design ◽

Low Leakage ◽

Sram Cell ◽

Improved Stability ◽

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Data-Retention Sleep Transistor CNTFET SRAM Cell Design at 32nm Technology for Low-Leakage

Mobile Communication and Power Engineering - Communications in Computer and Information Science ◽

10.1007/978-3-642-35864-7_54 ◽

2013 ◽

pp. 362-368

Author(s):

S. Rajendra Prasad ◽

B. K. Madhavi ◽

K. Lal Kishore

Keyword(s):

Cell Design ◽

Data Retention ◽

Low Leakage ◽

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Low-Leakage, Low-Power, High-Stable SRAM Cell Design

Advances in Intelligent Systems and Computing - Proceedings of the Second International Conference on Computer and Communication Technologies ◽

10.1007/978-81-322-2517-1_53 ◽

2015 ◽

pp. 549-556

Author(s):

Soumitra Pal ◽

Y. Krishna Madan ◽

Aminul Islam

Keyword(s):

Low Power ◽

Cell Design ◽

Low Leakage ◽

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A low leakage and SNM free SRAM cell design in deep sub micron CMOS technology

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06) ◽

10.1109/vlsid.2006.12 ◽

2006 ◽

Author(s):

S.K. Jain ◽

P. Agarwal

Keyword(s):

Cmos Technology ◽

Cell Design ◽

Low Leakage ◽

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Three-Dimensional Monolithic FinFET-Based 8T SRAM Cell Design for Enhanced Read Time and Low Leakage

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2018.2883525 ◽

2019 ◽

Vol 27 (4) ◽

pp. 899-912 ◽

Author(s):

Abdullah Guler ◽

Niraj K. Jha

Keyword(s):

Three Dimensional ◽

Cell Design ◽

Low Leakage ◽

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Low Leakage-Power SRAM Cell Design Using CNTFETs at 32nm Technology

Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering - Advances in Communication, Network, and Computing ◽

10.1007/978-3-642-35615-5_24 ◽

2012 ◽

pp. 165-171

Author(s):

Rajendra Prasad S. ◽

B. K. Madhavi ◽

K. Lal Kishore

Keyword(s):

Leakage Power ◽

Cell Design ◽

Low Leakage ◽

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Power optimized variation aware dual-threshold SRAM cell design technique

Nanotechnology Science and Applications ◽

10.2147/nsa.s15719 ◽

2011 ◽

pp. 25 ◽

Author(s):

Aminul Islam ◽

Mohd. Hasan ◽

Mohamed Hasan

Keyword(s):

Cell Design ◽

Design Technique ◽

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A low power 8T SRAM cell design technique for CNFET

2008 International SoC Design Conference ◽

10.1109/socdc.2008.4815601 ◽

2008 ◽

Author(s):

Young Bok Kim ◽

Yong-Bin Kim ◽

Fabrizio Lombardi ◽

Young Jun Lee

Keyword(s):

Low Power ◽

Cell Design ◽

Design Technique ◽

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