Novel SAT-Based Peak Dynamic Power Estimation for Digital Circuits

Journal of Low Power Electronics ◽

10.1166/jolpe.2009.1042 ◽

2009 ◽

Vol 5 (4) ◽

pp. 429-438 ◽

Author(s):

K. Shyamala ◽

J. Vimalkumar ◽

V. Kamakoti

Keyword(s):

Digital Circuits ◽

Power Estimation ◽

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Triple-bit method for power estimation of nonlinear digital circuits in FPGAs

Electronics Letters ◽

10.1049/el.2010.0790 ◽

2010 ◽

Vol 46 (13) ◽

pp. 903 ◽

Author(s):

B. Jovanovic ◽

R. Jevtic ◽

C. Carreras

Keyword(s):

Digital Circuits ◽

Power Estimation

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Modelling Macromodules for High-Level Dynamic Power Estimation of FPGA-based Digital Designs

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design ◽

10.1109/lpe.2006.4271826 ◽

2006 ◽

Author(s):

Axel Reimer ◽

Arne Schulz ◽

Wolfgang Nebel

Keyword(s):

Power Estimation ◽

Dynamic Power ◽

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Delay Constrained Register Transfer Level Dynamic Power Estimation

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/11847083_4 ◽

2006 ◽

pp. 36-46 ◽

Author(s):

Sriram Sambamurthy ◽

Jacob A. Abraham ◽

Raghuram S. Tupuri

Keyword(s):

Power Estimation ◽

Register Transfer Level ◽

Dynamic Power ◽

Register Transfer

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A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits

21st International Conference on VLSI Design (VLSID 2008) ◽

10.1109/vlsi.2008.56 ◽

2008 ◽

Author(s):

Sriram Sambamurthy ◽

Jacob A. Abraham ◽

Raghuram S. Tupuri

Keyword(s):

Power Estimation ◽

Register Transfer Level ◽

Sequential Circuits ◽

Top Down ◽

Dynamic Power ◽

Register Transfer

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Modelling macromodules for high-level dynamic power estimation of FPGA-based digital designs

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design ◽

10.1145/1165573.1165609 ◽

2006 ◽

Author(s):

Axel Reimer ◽

Arne Schulz ◽

Wolfgang Nebel

Keyword(s):

Power Estimation ◽

Dynamic Power ◽

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Operation Mode Based High-Level Switching Activity Analysis for Power Estimation of Digital Circuits

IEICE Transactions on Communications ◽

10.1093/ietcom/e90-b.7.1826 ◽

2007 ◽

Vol E90-B (7) ◽

pp. 1826-1834 ◽

Author(s):

H. SHIN ◽

C. LEE

Keyword(s):

Digital Circuits ◽

Operation Mode ◽

Power Estimation ◽

Activity Analysis ◽

Switching Activity ◽

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Dynamic Power Estimation for Motion Estimation Hardware

2011 14th Euromicro Conference on Digital System Design ◽

10.1109/dsd.2011.40 ◽

2011 ◽

Author(s):

Caglar Kalaycioglu ◽

Ilker Hamzaoglu

Keyword(s):

Motion Estimation ◽

Power Estimation ◽

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Dynamic power estimation using the probabilistic contribution measure (PCM)

Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477) ◽

10.1109/lpe.1999.799458 ◽

2003 ◽

Author(s):

Hoon-Sang Jin ◽

Myung-Soo Jang ◽

Jin-Suk Song ◽

Jin-Yong Lee ◽

Taek-Sao Ki ◽

...

Keyword(s):

Power Estimation ◽

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A Dynamic Power Estimation Method for System on Chip Designs

Journal of Low Power Electronics ◽

10.1166/jolpe.2015.1408 ◽

2015 ◽

Vol 11 (4) ◽

pp. 455-466 ◽

Author(s):

M. Karunaratne ◽

A. Sagahyroon

Keyword(s):

Estimation Method ◽

Power Estimation ◽

System On Chip ◽

Dynamic Power ◽

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Quantifying Error in Dynamic Power Estimation of CMOS Circuits

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-005-6759-4 ◽

2005 ◽

Vol 42 (3) ◽

pp. 253-264 ◽

Author(s):

Puneet Gupta ◽

Andrew B. Kahng ◽

Swamy Muddu

Keyword(s):

Power Estimation ◽

Cmos Circuits ◽

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