Simulation-Based Power Estimation for Low-Power Designs: A Fractal Approach

SIMULATION ◽  
1999 ◽  
Vol 72 (5) ◽  
pp. 320-326 ◽  
Author(s):  
Rajakrishnan Radjassamy ◽  
Jo Dale Carothers
Keyword(s):  
Low Power ◽  
Power Estimation ◽  
Fractal Approach ◽  
Simulation Based

scholarly journals Accurate Estimation of Power Consumption for Binary Comparator System using Back Tracking

2021 ◽  
Vol 19 (2) ◽  
Author(s):  
Mangal Deep Gupta ◽  
‪Rajeev Kumar Chauhan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Timing Analysis ◽  
Logic Gates ◽  
Power Estimation ◽  
Accurate Estimation ◽  
Worst Case ◽  
Simulation Based ◽  
Tracking Model ◽  
Power Delay Product

This paper presents a design of a binary comparator circuit using minimum fan-in logic gates (NAND-NOR) for achieving low power-delay-product (PDP). A 2-bit binary comparator circuit is re-designed to minimize fan-in of logic gates. Utilizing the concept of 2–bit comparator, a general gate-level architecture of a comparator system is proposed for higher input operands. A back-tracking model has been proposed in this work to estimate the worst-case performance in terms of delay and power or PDP for binary comparator circuits. It combines the advantages of the simulation-based method for power estimation and dynamic timing analysis (DTA) techniques for timing analysis. This work has also been extended for 20, 16, 14, 10, and 7-nm FINFET technology. The comparator circuits are simulated on Pyxis schematic tool by Mentor Graphics.

Micro-Power Wireless CSMA/CA Algorithm Improvement and Simulation Based on the Electric Power Business

2014 ◽  
Vol 494-495 ◽  
pp. 1640-1646
Author(s):  
Yu Lan ◽  
Xin Lu ◽  
Ye Shen He ◽  
Yun Feng Li
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Collision Detection ◽  
Wireless Transmission ◽  
Low Power Consumption ◽  
Mac Layer ◽  
Electric System ◽  
Simulation Based ◽  
Micro Power ◽  
Fixed Power

In the micro-power wireless transmission of the electric system, positions among modes are relatively fixed, power business data is reported at specific time points, and time distribution presents great differences. Key technologies of IEEE802.15.4 MAC layer protocol is expounded, shortages of collision detection and CSMA/CA on power business support, etc. are discussed, self-adaptive low-power consumption CSMA/CA algorithm which is more suitable for business of the electric system are designed and improved, and the algorithm goes through simulation experiment against the business characteristics of micro-power wireless network of the electric system. The simulation result demonstrates the algorithm may be greatly adapted to changes of network traffic under a relatively fixed environment of network topology on the premise of low power consumption.

More Precise FPGA Power Estimation and Validation Tool (FPEV_Tool) for Low Power Applications

2018 ◽  
Vol 106 (4) ◽  
pp. 2237-2246 ◽  
Author(s):  
Gaurav Verma ◽  
Vijay Khare ◽  
Manish Kumar
Keyword(s):  
Low Power ◽  
Power Estimation ◽  
Validation Tool

Power estimation strategies for a low-power security processor

2005 ◽  
Author(s):  
Yen-Fong Lee ◽  
Shi-Yu Huang ◽  
Sheng-Yu Hsu ◽  
I-Ling Chen ◽  
Cheng-Tao Shieh ◽  
...  
Keyword(s):  
Low Power ◽  
Power Estimation ◽  
Security Processor

scholarly journals Modeling and Implementation of a Power Estimation Methodology for SystemC

2012 ◽  
Vol 2012 ◽  
pp. 1-12 ◽  
Author(s):  
Matthias Kuehnle ◽  
Andre Wagner ◽  
Alisson V. Brito ◽  
Juergen Becker
Keyword(s):  
Power Analysis ◽  
Input Data ◽  
Power Estimation ◽  
System Level ◽  
Power Monitoring ◽  
Simulation Based ◽  
Speed Up ◽  
Logic Modules ◽  
Implicit Power ◽  
Power Evaluation

This work describes a methodology to model power consumption of logic modules. A detailed mathematical model is presented and incorporated in a tool for translation of models written in VHDL to SystemC. The functionality for implicit power monitoring and estimation is inserted at module translation. The translation further implements an approach to wrap RTL to TLM interfaces so that the translated module can be connected to a system-level simulator. The power analysis is based on a statistical model of the underlying HW structure and an analysis of input data. The flexibility of the C++ syntax is exploited, to integrate the power evaluation technique. The accuracy and speed-up of the approach are illustrated and compared to a conventional power analysis flow using PPR simulation, based on Xilinx technology.

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