scholarly journals Continuous energy consumption measure approach using a DMA double-buffering technique

Author(s):  
Daniel Vaquerizo-Hdez ◽  
Pablo Muñoz ◽  
David F. Barrero ◽  
Maria D. R-Moreno

AbstractMeasuring the consumption of electronic devices is a difficult and sensitive task. Data acquisition (DAQ) systems are often used to determine such consumption. In theory, measuring energy consumption is straight forward, just by acquiring current and voltage signals we can determine the consumption. However, a number of issues arise when a fine analysis is required. The main problem is that sampling frequencies have to be high enough to detect variations in the assessed signals over time. In that regard, some popular DAQ systems are based on RISC ARM processors for microcontrollers combined with analog-to-digital converters to meet high-frequency acquisition requirements. The efficient use of direct memory access (DMA) modules combined with pipelined processing in a microcontroller allows to improve the sample rate overcoming the processing time and the internal communication protocol limitations. This paper presents a novel approach for high-frequency energy measurement composed of a DMA rate improvement (data acquisition logic), a data processing logic and a low-cost hardware. The contribution of the paper is the combination of a double-buffered signal acquisition mechanism and an algorithm that computes the device’s energy consumption using parallel data processing. The combination of these elements enables a high-frequency (continuous) energy consumption measurement of an electronic device, improving the accuracy and reducing the cost of existing systems. We have validated our approach by measuring the energy consumed by elemental circuits and wireless sensors networks (WSNs) motes. The results indicate that the energy measurement error is less than 5% and that the proposed method is suitable to measure WSN motes even during sleep cycles, enabling a better characterization of their consumption profile.

2020 ◽  
Author(s):  
Daniel Vaquerizo Hernández ◽  
Pablo Munoz ◽  
David Fernandez Barrero ◽  
Maria Dolores R-Moreno

Abstract Measuring the consumption of electronic devices is a difficult and sensitive task. Data AcQuisition (DAQ) systems are often used to determine such consumption. In theory, measuring energy consumption is straightforward, just by acquiring current and voltage signals we can determine the consumption. However, a number of issues arise when a ne analysis is required. The main problem is that sampling frequencies have to be high enough to detect variations in the assessed signals over time. In that regard, some popular DAQ systems are based on RISC ARM processors for microcontrollers combined with Analog-Digital Converters (ADC) to meet the frequency acquisition requirements. The efficient use of the Direct Memory Access (DMA) modules combined with pipelined processing in the microcontroller allows to improve the sample rate overcoming the processing time and the internal communication protocol limitations. This paper presents a novel approach for high frequency energy measurement composed of a DMA rate improvement (data acquisition logic), a data processing logic and a low-cost hardware. The contribution of the paper is the combination of a double buffered signal acquisition mechanism and an algorithm that computes the device's energy consumption using parallel data processing. The combination of these elements enables a high-frequency (continuous) energy consumption measurement of an electronic device, improving the accuracy and reducing the cost of existing systems. We have validated our approach by measuring the energy consumed by basic circuits and Wireless Sensors Networks (WSNs) motes. The results indicate that the energy measurement error is less than 5%, and that the proposed method is suitable to measure WSN motes even during sleep cycles, enabling a better characterization of their consumption prole.


2011 ◽  
Vol 383-390 ◽  
pp. 497-502
Author(s):  
Guo Ku Zhao ◽  
Shu Shi Ning ◽  
Zhao Wei Cai ◽  
Ze Qian Xu

In order to improve the accuracy of the underwater acoustic detection effectively, the digital signal acquisition circuxcA`\\it is a necessary deceive, which must have enough high data acquisition rate. Therefore the high frequency operating clock is employed in the traditional digital signal acquisition circuit. However, the high frequency operating clock will bring troubles to the design of hardware and software, and the power consumption and interference of the system are both increased. According to the principle of the pipelined system, the operation of AD deceive is divided into two process, including the conversion starting and data reading. The FPGA is employed to produce control signals which make twin-AD work in proper state. The design of the underwater acoustic signal acquisition system based on the pipelined twin-AD is presented here. On the base of the system design, simulation, implementation, the hardware experiments are completed. The results show: driven by the operating clock with same frequency, the underwater acoustic signal acquisition system based on the pipelined twin-AD can obtain the acquisition rate which is twice as the traditional data acquisition system.


Sensors ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1128
Author(s):  
Yang Bai ◽  
Xin Zhang ◽  
Qiang Yang ◽  
Yong Yang ◽  
Weibo Deng ◽  
...  

It is known that the data acquisition and processing system plays an important role in radar target detection system. In order to meet the requirements of real-time processing and accurate transmission of echo signals in high-frequency ground-wave radar (HFGWR) systems, a new acquisition and transmission framework utilizing the designed acquisition card based on the PCIe (peripheral component interconnect express) has been designed and is presented in this paper. The Xilinx FPGA (Field-Programmable Gate Array) chip Kintex7-XC7K325T is adopted as a hardware carrier in acquisition card. The hardware’s composition, analog front-end circuit, the DMA (Direct Memory Access) transmission, FPGA structure, ADC (Analog-to-Digital Converter) chip, and performance test of this card are showed and discussed. Currently, the acquisition card has been accomplished and applied in the practical system of HFGWR.


2021 ◽  
Vol 1826 (1) ◽  
pp. 012082
Author(s):  
G F Bassous ◽  
R F Calili ◽  
C R H Barbosa

2012 ◽  
Vol 546-547 ◽  
pp. 1393-1397
Author(s):  
Zhi Wen Xiong ◽  
Chen Guang Xu ◽  
Hong Zeng

Data acquisition begins with the physical phenomenon or physical property to be measured. Examples of this include temperature, gas pressure, and light intensity, and force, fluid flow, regardless of the type of physical property to be measured. Physical property converted into digital, and then by the computer for storage, processing, display or printing process, the corresponding system is called data acquisition system. With the rapid development of computer technology, data acquisition systems quickly gained popularity. A variety of products based on digital technology have been created. Digital System spread quickly; it’s mainly the following two advantages: the first is the digital processing flexible and convenient; the second is a digital system is very reliable. The main idea of Reconfigurable computing technology [1] is using the FPGA [2][3] allows the system has a dynamically configurable capacity, suitable for harsh environment applications, improve the speed of data processing. By the use of dynamic reconfigurable FPGA devices can be realized on the hardware logic function modification, application of reconfigurable computing technology can improve the speed of data processing. Data acquisition system is widely applied in many fields, and often used the abominable working environment place. The reconfigurable computing technology, can greatly improve the data acquisition system reliability and safety. The paper introduces a kind of multi-channel data acquisition system based on USB bus and FPGA, the factors affecting the performance of system are discussed, and describes how to use reconfigurable computing technology to improve the efficiency of data acquisition system while reduce energy consumption. The system in this paper uses AD's AD9220, ALTERA's EP1C6-8 and IDT's IDT70V24, Cypress’s CY7C68013.


2016 ◽  
Vol 2016 ◽  
pp. 1-14 ◽  
Author(s):  
Glauco Feltrin ◽  
Nemanja Popovic ◽  
Kallirroi Flouri ◽  
Piotr Pietrzak

Wireless sensor networks have been shown to be a cost-effective monitoring tool for many applications on civil structures. Strain cycle monitoring for fatigue life assessment of railway bridges, however, is still a challenge since it is data intensive and requires a reliable operation for several weeks or months. In addition, sensing with electrical resistance strain gauges is expensive in terms of energy consumption. The induced reduction of battery lifetime of sensor nodes increases the maintenance costs and reduces the competitiveness of wireless sensor networks. To overcome this drawback, a signal conditioning hardware was designed that is able to significantly reduce the energy consumption. Furthermore, the communication overhead is reduced to a sustainable level by using an embedded data processing algorithm that extracts the strain cycles from the raw data. Finally, a simple software triggering mechanism that identifies events enabled the discrimination of useful measurements from idle data, thus increasing the efficiency of data processing. The wireless monitoring system was tested on a railway bridge for two weeks. The monitoring system demonstrated a good reliability and provided high quality data.


Sign in / Sign up

Export Citation Format

Share Document