Four-Channel Hybrid Silicon Laser Array with low power consumption for on-chip optical interconnects

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

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Reconfigurable on-chip communication link for efficient communication

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i2.9760 ◽

2018 ◽

Vol 7 (2-1) ◽

pp. 417

Author(s):

Beulah Hemalatha S ◽

Vigneswaran T

Keyword(s):

Genetic Algorithm ◽

Power Consumption ◽

Low Power ◽

Optimization Problems ◽

Research Area ◽

Low Power Consumption ◽

Communication Link ◽

Simulated System ◽

Efficient Communication ◽

On Chip

Application specific reconfiguration of On-chip communication link is a fast growing research area in system on chip (SoC) based system design. Optimization of the communication link is important to achieve a trade-off between efficient communication and low power consumption. So achieving both efficient communication and low power consumption requires a special optimization mechanism. Such Optimization problems can be solved using a genetic algorithm. Here, in this paper genetic algorithm based On-chip communication link reconfiguration is presented. The algorithm will optimize efficiency of communication link with constrain of low power consumption. The parameters involved in power consumption and efficient communication link are coded in the chromosomes. By evolutionary iteration the optimal parameters of the communication link are derived that is used for the communication link successfully in the simulated system. The performance of the simulated system is analyzed which shows the out performance of the proposed system.

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Design of Completion Detectors in Asynchronous Communication System

International Journal of Innovative Technology and Exploring Engineering - Special Issue ◽

10.35940/ijitee.c8576.019320 ◽

2020 ◽

Vol 9 (3) ◽

pp. 3329-3334

Keyword(s):

Power Consumption ◽

Low Power ◽

Communication System ◽

Implementation Process ◽

Asynchronous Communication ◽

Digital Design ◽

Low Power Consumption ◽

Asynchronous Design ◽

Global Clock ◽

On Chip

In digital design, there are two types of design, synchronous design and asynchronous design. In synchronous design, global clock is one of the main system that consume a lot of power. The power in synchronous design is consumed by clock even if there is no data processing take place. The asynchronous design that depends on data is clockless and as far as the power is concerned, asynchronous design does not consume much power compared with synchronous design and this really make asynchronus design the preffered choice for low power consumption. Besides having low power consumption, there are many advantages of aynchronous design compared with synchronous design. This paper proposed new dual rail completion detector (CD), 3-6 CD, 2-7 CD and 1-4 CD for on-chip communication that are used widely in an asynchronous communication system. The design of CD is based on the principle of sum adder. The circuit is designed by using Altera Quartus II CAD tools, synthesis and implementation process is executed to check the syntax error of the design. The design proved to be successful by using asynchronous on-chip communication in the simulation.

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