scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

A NOVEL SWITCHED-CURRENT SUCCESSIVE APPROXIMATION ADC

2011 ◽  
Vol 20 (01) ◽  
pp. 15-27 ◽  
Author(s):  
XIAN TANG ◽  
KONG PANG PUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
High Speed ◽  
High Accuracy ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Power Efficient ◽  
Successive Approximation Adc ◽  
Switched Current

A novel switched-current successive approximation ADC is presented in this paper with high speed and low power consumption. The proposed ADC contains a new high-accuracy and power-efficient switched-current S/H circuit and a speed-improved current comparator. Designed and simulated in a 0.18-μm CMOS process, this 8-bit ADC achieves 46.23 dB SNDR at 1.23 MS/s consuming 73.19 μW under 1.2 V voltage supply, resulting in an ENOB of 7.38-bit and an FOM of 0.357 pJ/Conv.-step.

Low-power consumption seamless wireless and wired links using transparent waveform transfer

2014 ◽  
Vol 3 (5-6) ◽  
Author(s):  
Tetsuya Kawanishi
Keyword(s):  
Power Consumption ◽  
Optical Fiber ◽  
Low Power ◽  
Millimeter Wave ◽  
Optical Fibers ◽  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
Low Power Consumption ◽  
Wireless Links

AbstractThis paper describes wired and wireless seamless networks consisting of radiowave and optical fiber links. Digital coherent technology developed for high-speed optical fiber transmission can mitigate signal deformation in radiowave links in the air as well as in optical fibers. Radio-over-fiber (RoF) technique, which transmits radio waveforms on intensity envelops of optical signals, can provide direct waveform transfer between optical and radio signals by using optical-to-electric or electric-to-optical conversion devices. Combination of RoF in millimeter-wave bands and digital coherent with high-performance digital signal processing (DSP) can provide wired and wireless seamless links where bit rate of wireless links would be close to 100 Gb/s. Millimeter-wave transmission distance would be shorter than a few kilometers due to large atmospheric attenuation, so that many moderate distance wireless links, which are seamlessly connected to optical fiber networks should be required to provide high-speed mobile-capable networks. In such systems, reduction of power consumption at media converters connecting wired and wireless links would be very important to pursue both low-power consumption and large capacity.

scholarly journals A 6-bit Low-Power High-Speed Flash ADC using 180 nm CMOS process

2014 ◽  
Vol 17 (1) ◽  
pp. 52-61
Author(s):  
Thanh Tri Vo ◽  
Trong Tu Bui ◽  
Duc Hung Le ◽  
Cong Kha Pham
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Sampling Rate ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Flash Adc ◽  
High Sampling Rate ◽  
Simulation Results

In this paper we present a design of Flash-ADC that can achieve high performance and low power consumption. By using the Double Sampling Rate technique and a new comparator topology with low kick-back noise, this design can achieve high sampling rate while still consuming low power. The design is implemented in a 0.18 m CMOS process. The simulation results show that this design can work at 400 MSps and power consumption is only 16.24 mW. The DNL and INL are 0.15 LSB and 0.6 LSB, respectively.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

scholarly journals A high-speed hybrid Full Adder with low power consumption

2012 ◽  
Vol 9 (24) ◽  
pp. 1900-1905
Author(s):  
Kamran Delfan Hemmati ◽  
Mojtaba Behzad Fallahpour ◽  
Abbas Golmakani ◽  
Kamyar Delfan Hemmati
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Full Adder ◽  
Low Power Consumption

scholarly journals Reconfigurable on-chip communication link for efficient communication

2018 ◽  
Vol 7 (2-1) ◽  
pp. 417
Author(s):  
Beulah Hemalatha S ◽  
Vigneswaran T
Keyword(s):  
Genetic Algorithm ◽  
Power Consumption ◽  
Low Power ◽  
Optimization Problems ◽  
Research Area ◽  
Low Power Consumption ◽  
Communication Link ◽  
Simulated System ◽  
Efficient Communication ◽  
On Chip

Application specific reconfiguration of On-chip communication link is a fast growing research area in system on chip (SoC) based system design. Optimization of the communication link is important to achieve a trade-off between efficient communication and low power consumption. So achieving both efficient communication and low power consumption requires a special optimization mechanism. Such Optimization problems can be solved using a genetic algorithm. Here, in this paper genetic algorithm based On-chip communication link reconfiguration is presented. The algorithm will optimize efficiency of communication link with constrain of low power consumption. The parameters involved in power consumption and efficient communication link are coded in the chromosomes. By evolutionary iteration the optimal parameters of the communication link are derived that is used for the communication link successfully in the simulated system. The performance of the simulated system is analyzed which shows the out performance of the proposed system.

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

scholarly journals Design of Completion Detectors in Asynchronous Communication System

2020 ◽  
Vol 9 (3) ◽  
pp. 3329-3334
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Communication System ◽  
Implementation Process ◽  
Asynchronous Communication ◽  
Digital Design ◽  
Low Power Consumption ◽  
Asynchronous Design ◽  
Global Clock ◽  
On Chip

In digital design, there are two types of design, synchronous design and asynchronous design. In synchronous design, global clock is one of the main system that consume a lot of power. The power in synchronous design is consumed by clock even if there is no data processing take place. The asynchronous design that depends on data is clockless and as far as the power is concerned, asynchronous design does not consume much power compared with synchronous design and this really make asynchronus design the preffered choice for low power consumption. Besides having low power consumption, there are many advantages of aynchronous design compared with synchronous design. This paper proposed new dual rail completion detector (CD), 3-6 CD, 2-7 CD and 1-4 CD for on-chip communication that are used widely in an asynchronous communication system. The design of CD is based on the principle of sum adder. The circuit is designed by using Altera Quartus II CAD tools, synthesis and implementation process is executed to check the syntax error of the design. The design proved to be successful by using asynchronous on-chip communication in the simulation.

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