ML-based Soft-failure Localization with Partial SDN Telemetry

Author(s):  
Kayol Mayer ◽  
Jonathan Soares ◽  
Rossano Pinto ◽  
Christian Rothenberg ◽  
Dalton Arantes ◽  
...  
Author(s):  
Kayol S. Mayer ◽  
Jonathan A. Soares ◽  
Rossano P. Pinto ◽  
Christian E. Rothenberg ◽  
Dalton S. Arantes ◽  
...  

2021 ◽  
Author(s):  
Rossano P. Pinto ◽  
Kayol S. Mayer ◽  
Jonathan A. Soares ◽  
Dalton S. Arantes ◽  
Darli A. A. Mello ◽  
...  

Author(s):  
Alba P. Vela ◽  
Behnam Shariati ◽  
Marc Ruiz ◽  
Jaume Comellas ◽  
Luis Velasco

2017 ◽  
Vol 10 (1) ◽  
pp. A27 ◽  
Author(s):  
A. P. Vela ◽  
B. Shariati ◽  
M. Ruiz ◽  
F. Cugini ◽  
A. Castro ◽  
...  

Author(s):  
Natsuko Asano ◽  
Shunsuke Asahina ◽  
Natasha Erdman

Abstract Voltage contrast (VC) observation using a scanning electron microscope (SEM) or a focused ion beam (FIB) is a common failure analysis technique for semiconductor devices.[1] The VC information allows understanding of failure localization issues. In general, VC images are acquired using secondary electrons (SEs) from a sample surface at an acceleration voltage of 0.8–2.0 kV in SEM. In this study, we aimed to find an optimized electron energy range for VC acquisition using Auger electron spectroscopy (AES) for quantitative understanding.


Author(s):  
I. Österreicher ◽  
S. Eckl ◽  
B. Tippelt ◽  
S. Döring ◽  
R. Prang ◽  
...  

Abstract Depending on the field of application the ICs have to meet requirements that differ strongly from product to product, although they may be manufactured with similar technologies. In this paper a study of a failure mode is presented that occurs on chips which have passed all functional tests. Small differences in current consumption depending on the state of an applied pattern (delta Iddq measurement) are analyzed, although these differences are clearly within the usual specs. The challenge to apply the existing failure analysis techniques to these new fail modes is explained. The complete analysis flow from electrical test and Global Failure Localization to visualization is shown. The failure is localized by means of photon emission microscopy, further analyzed by Atomic Force Probing, and then visualized by SEM and TEM imaging.


Author(s):  
Chuan Zhang ◽  
Yinzhe Ma ◽  
Gregory Dabney ◽  
Oh Chong Khiam ◽  
Esther P.Y. Chen

Abstract Soft failures are among the most challenging yield detractors. They typically show test parameter sensitive characteristics, which would pass under certain test conditions but fail under other conditions. Conductive-atomic force microscopy (CAFM) emerged as an ideal solution for soft failure analysis that can balance the time and thoroughness. By inserting CAFM into the soft failure analysis flow, success rate of such type of analysis can be significantly enhanced. In this paper, a logic chain soft failure and a SRAM local bitline soft failure are used as examples to illustrate how this failure analysis methodology provides a powerful and efficient solution for soft failure analysis.


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