Analysis of Delta Iddq Soft Fails on Pass Chips

2006 ◽  
Author(s):  
I. Österreicher ◽  
S. Eckl ◽  
B. Tippelt ◽  
S. Döring ◽  
R. Prang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mode ◽  
Photon Emission ◽  
Complete Analysis ◽  
Functional Tests ◽  
Analysis Techniques ◽  
Atomic Force ◽  
Current Consumption ◽  
Emission Microscopy ◽  
Failure Localization

Abstract Depending on the field of application the ICs have to meet requirements that differ strongly from product to product, although they may be manufactured with similar technologies. In this paper a study of a failure mode is presented that occurs on chips which have passed all functional tests. Small differences in current consumption depending on the state of an applied pattern (delta Iddq measurement) are analyzed, although these differences are clearly within the usual specs. The challenge to apply the existing failure analysis techniques to these new fail modes is explained. The complete analysis flow from electrical test and Global Failure Localization to visualization is shown. The failure is localized by means of photon emission microscopy, further analyzed by Atomic Force Probing, and then visualized by SEM and TEM imaging.

SRAM Failure Analysis Strategy

2003 ◽  
Author(s):  
P. Egger ◽  
C. Burmer
Keyword(s):  
Liquid Crystal ◽  
Failure Analysis ◽  
The Other ◽  
Other Hand ◽  
Analysis Strategy ◽  
Emission Microscopy ◽  
Metal Layers ◽  
Failure Localization

Abstract The area of embedded SRAMs in advanced logic ICs is increasing more and more. On the other hand smaller structure sizes and an increasing number of metal layers make conventional failure localization by using emission microscopy or liquid crystal inefficient. In this paper a SRAM failure analysis strategy will be presented independent on layout and technology.

Study of Thermal Cycle Induced CPI Failure Mode in a Lidded FC-BGA Package

2019 ◽  
Author(s):  
Muhammad Monzur Morshed ◽  
Esther Chen ◽  
Anita Madan
Keyword(s):  
Failure Analysis ◽  
Failure Mode ◽  
Failure Modes ◽  
Material Selection ◽  
Interfacial Stress ◽  
Analysis Techniques ◽  
Bga Package ◽  
Induced Defects ◽  
Fatigue Failures ◽  
Insight Into

Abstract Dissimilarities of thermal expansion coefficient between chip and package materials results in stress and strain at the solder interconnect leading to fatigue failures. Underfill is used between chip and package to reduce the interfacial stress and hence increase reliability. In this work, four flipchip package test vehicles underwent thermal cycling to accelerate the stress and were investigated systematically with different failure analysis techniques to study their failure modes. The prevalent failure mode was observed to be at the corner area between the chip and package using different advanced failure analysis techniques. This work demonstrates the technical complexity of analyzing stress induced defects and provides insight into CPI-based material selection.

Coupling C-AFM with Nanoprobing Technique for Further Junction Leakage Analysis

2006 ◽  
Author(s):  
Cha-Ming Shen ◽  
Tsan-Chen Chuang ◽  
Chen-May Huang ◽  
Shi-Chen Lin ◽  
Jie-Fei Chang
Keyword(s):  
Failure Analysis ◽  
Atomic Force Microscope ◽  
Failure Modes ◽  
Electrical Characteristic ◽  
Failure Mechanisms ◽  
Gate Leakage ◽  
Process Technology ◽  
Analysis Techniques ◽  
Atomic Force ◽  
Or Gate

Abstract With the evolution of advanced process technology, failure analysis has become more and more difficult because more defects are of the non-visual type (very tiny or even invisible defects) from new failure mechanisms. In this article, a novel and effective methodology which couples the conductive atomic force microscope (C-AFM) with nano-probing technique is proposed to reveal some particular failure modes which were not observable and difficult to identify with traditional physical failure analysis techniques. The capability of coupling C-AFM with nano-probing technique is used to distinguish cases which suffer general junction leakage or gate leakage from those that form the fake junction leakage or gate leakage cases. C-AFM can detect the abnormal contacts quickly, and nano-probing could provide the precise electrical characteristic further. Then, combining these variant measuring results, the favorable tactics can be adopted to deal with different states.

Failure Analysis Methodology on Resistive Open Defects

2014 ◽  
Author(s):  
A.C.T. Quah ◽  
G.B. Ang ◽  
D. Nagalingam ◽  
C.Q. Chen ◽  
H.P. Ng ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Photon Emission ◽  
Analysis Methodology ◽  
Failure Path ◽  
Open Defect ◽  
Emission Microscopy ◽  
Open Defects ◽  
Logic Array ◽  
Failure Site

Abstract This paper describes the observation of photoemissions from saturated transistors along a connecting path with open defect in the logic array. By exploiting this characteristic phenomenon to distinguish open related issues, we described with 2 case studies using Photon Emission Microscopy, CAD navigation and layout tracing to identify the ‘open’ failure path. Further layout and EBAC analysis are then employed to effectively localize the failure site.

Failure Analysis of SOI Bipolar Device Using Photon Emission Microscopy

2004 ◽  
Author(s):  
Todd M. Simons ◽  
Bob Davis
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Silicon On Insulator ◽  
The Other ◽  
No Emission ◽  
Analysis Process ◽  
Soi Devices ◽  
Emission Microscopy ◽  
Optical Paths

Abstract Photon emission microscopy (PEM) provides a valuable first step in the failure analysis process. An analysis of a mixed signal bipolar/CMOS silicon on insulator (SOI) device revealed an abnormal emission site that appeared to emanate from the oxide isolation ring. Subsequent mechanical probing of the emitting bipolar transistor revealed node voltages nearly identical to a known good reference unit that had no emission site at the affected transistor. This article analyzes the reasons for the emission site on one transistor and not the other even though the node voltages were the same. It was observed that while the node voltages were nearly identical, the available current paths were not. The different paths directly related to the amount of available carriers for recombination in the base. The construction of the SOI device creates unique optical paths for emission sites not observed in non-SOI devices. It can be concluded that the failure mechanism does not always reside at the abnormal PEM site.

ESD Failure Analysis and Robustness Design in Vertical-Diffused MOS Transistors

2014 ◽  
Vol 926-930 ◽  
pp. 456-461
Author(s):  
Shen Li Chen ◽  
Wen Ming Lee ◽  
Chi Ling Chu
Keyword(s):  
Failure Analysis ◽  
Oxide Layer ◽  
Failure Mode ◽  
Epitaxial Layer ◽  
Gate Oxide ◽  
The Other ◽  
Mos Transistors ◽  
Oxide Breakdown ◽  
Analysis Techniques ◽  
Silicon Epitaxial Layer

This paper deals with a detailed study of ESD failure mode and how to strengthen of the VDMOS used for power applications. The ESD post-zapped failure of power VDMOS transistors due to HBM, MM, and CDM stresses are examined in this work. Through standard failure analysis techniques by using EMMI and SEM were applied to identify the failure locations. The MM failure mode in this power MOSFET was caused by the gate oxide breakdown near n+ region in the source end as an ESD zapping. And, the ESD failure damage under HBM and CDM stresses were caused by the gate material molten near the gate pad and tunneled through the oxide layer into silicon epitaxial layer. Furthermore, the ESD robustness designs of power VDMOS transistors are also addressed in this work. The first ESD incorporated design is Zener diodes back-to-back clamping the gate-to-source pad, and on the other hand, another one excellent design contains two Zener diodes clamping the gate-to-source and gate-to-drain terminals of a VDMOS, respectively.

Failure Analysis of Sub-Micron Semiconductor Integrated Circuit Using Backside Photon Emission Microscopy

1999 ◽  
Author(s):  
Soon Lim ◽  
Jian Hua Bi ◽  
Lian Choo Goh ◽  
Soh Ping Neo ◽  
Sudhindra Tatti
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Photon Emission ◽  
Fault Isolation ◽  
Integrated Circuit Fabrication ◽  
Circuit Fabrication ◽  
Emission Microscopy ◽  
On Chip

Abstract The progress of modern day integrated circuit fabrication technology and packaging has made fault isolation using conventional emission microscopy via the top of the integrated circuit more difficult, if not impossible. This is primarily due to the use of increased levels and density of metal-interconnect, and the advent of new packaging technology, e.g. flip-chip, ball-grid array and lead-on-chip, etc. Backside photon emission microscopy, i.e. performing photon emission microscopy through the bulk of the silicon via the back of the integrated circuit is a solution to this problem. This paper outlines the failure analysis of sub-micron silicon integrated circuits using backside photon emission microscopy. Sample preparation, practical difficulties encountered and case histories will be discussed.

Effectiveness of Emission Microscopy in the Failure Analysis of CMOS ASIC Devices

1997 ◽  
Author(s):  
K. H. Parekh ◽  
R. Milburn
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Photon Emission ◽  
Reliability Test ◽  
Input Output ◽  
End User ◽  
Final Test ◽  
Leakage Currents ◽  
Emission Microscopy ◽  
Scanning Electron

Abstract In the last several years emission microscopy has become an essential tool for failure analysis, specifically for VLSI devices. This paper describes various die related failure mechanisms in CMOS ASIC devices which were detected by emission microscopy. The failure analysis results discussed in this paper are primarily of the devices which were analyzed over the period of the last three years, 1994 - 1996. These devices were from a broad spectrum of final test failures, qualification and reliability test failures, special evaluation failures, testing and assembly failures at customer sites, and end user field failures. In addition to the failure mechanism statistic scanning electron micrographic illustrations of some of the failure mechanisms and associated damage are presented in this paper. The data presented in this paper clearly show the effectiveness of photon emission microscopy. The value of emission microscopy really lies in quick detection of failure locations on the die which failed functionally or due to excessive static IOD, functional IOD, or input/output leakage currents. It has certainly impacted tum around time of the analysis as significant reduction in analysis time has been achieved. In some cases same day turn around was possible.

Accelerating Technology Development and Yield Ramp on First Silicon Utilizing a Wafer-Level Dynamic EFA System

2016 ◽  
Author(s):  
Li-Qing Chen ◽  
Ming-Sheng Sun ◽  
Jui-Hao Chao ◽  
Soon Fatt Ng ◽  
Kapilevich Izak ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
Photon Emission ◽  
Wafer Level ◽  
Success Story ◽  
Electrical Failure ◽  
Analysis Techniques ◽  
Soft Failure ◽  
Scan Chain ◽  
Hard Failure

Abstract This paper presents the success story of the learning process by reporting four cases using four different failure analysis techniques. The cases covered are IDDQ leakage, power short, scan chain hard failure, and register soft failure. Hardware involved in the cases discussed are Meridian WS-DP, a wafer-level electrical failure analysis (EFA) system from DCG Systems, V9300 tester from Advantest, and a custom cable interface integrating WSDP and V9300 with the adaption of direct-probe platform that is widely deployed for SoC CP test. Four debug cases are reported in which various EFA techniques are proven powerful and effective, including photon emission, OBIRCH, Thermal Frequency Imaging, LVI, LVP, and dynamic laser stimulation.

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