Spatial Oversampling to overcome High-speed ADC Noise Limited Performance

Author(s):  
Dan M. Marom ◽  
Ori Golani
Keyword(s):  
2015 ◽  
Vol 719-720 ◽  
pp. 534-537
Author(s):  
Wen Hua Ye ◽  
Huan Li

With the development of digital signal processing technology, the demand on the signal processor speed has become increasingly high. This paper describes the hardware design of carrier board in high-speed signal processing module, which using Xilinx's newest Virtex-7 FPGA family XC7VX485T chip, and applying high-speed signal processing interface FMC to transport and communicate high-speed data between carrier board and daughter card with high-speed ADC and DAC. This design provides a hardware implementation and algorithm verification platform for high-speed digital signal processing system.


2015 ◽  
Vol 65 (6) ◽  
pp. 472 ◽  
Author(s):  
M. Sreenivasa Rao ◽  
Chandan C. Mishra ◽  
K. Krishna Naik ◽  
K. Maheshwara Reddy

Electronic warfare receiver works in the wide electromagnetic spectrum in dense radar signal environment. Current trends in radar systems are ultra wideband and low probability of intercept radar technology. Detection of signals from various radar stations is a concern. Performance and probability of intercept are mainly dependent on high speed ADC technology. The sampling and reconstruction functions have to be optimized to capture incoming signals at the receiver to extract characteristics of the radar signal. The compressive sampling of the input signal with orthonormal base vectors, projecting the basis in the union of subspaces and recovery through convex optimisation techniques is the current traditional approach. Modern trends in signal processing suggest the random modulator pre-integrator (RMPI), which sample the input signal at information rate non-adaptively and recovery by the processing of discrete and finite vectors. Analysis of RMPI theory, application to EW receiver, simulation and recovery of EW receiver signals are discussed.


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