scholarly journals Bit wise and delay of vedic multiplier

2017 ◽  
Vol 7 (1.5) ◽  
pp. 26
Author(s):  
M Siva Kumar ◽  
Sanath Kumar Tulasi ◽  
N Srinivasulu ◽  
Vijaya Lakshmi Bandi ◽  
K Hari Kishore
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Digital Signal ◽  
Vedic Mathematics ◽  
Whole Process ◽  
Vedic Multiplier ◽  
Mode Of Operation ◽  
Wave Forms ◽  
Ancient Mathematics ◽  
Binary Addition

The Vedic multiplier is derived from the ancient mathematics called Vedic mathematics .The ancient mathematics has different sutras in that we use Urdhva Tiryagbhyam sutra which means clock wise and vertically . As we know that binary multiplication is not possible so that instead we use binary addition or subtraction instead of it. The key process for the multiplication is the speed of the processor. The fastest mode of multiplication is the Vedic multiplier. In this paper we want to show the delay and utilization of components available for the multiplier by executing the code. The comparison of delay from some papers was also proposed in this paper. The research is going on the Vedic mathematics to overcome the problems on the conventional mathematics. In future Vedic multiplier plays an important role in the DSP (Digital Signal Processing).As it is the fastest and efficient mode of operation. In this paper I am calculating the bit wise delay up to 32-bit. The whole analysis was done in Xilinx. The ISM wave forms for every bit up to 32-bit was to be obtained. The utilization, used, available, utilized analysis was also taken. The whole process was done in XILINX software.

Characterization of Granular Systems by Digital Signal Processing of Low Strain Wave Response

1996 ◽  
Vol 1548 (1) ◽  
pp. 38-45
Author(s):  
Salome Romero ◽  
Sibel Pamukcu
Keyword(s):  
Signal Processing ◽  
Shear Modulus ◽  
Digital Signal Processing ◽  
Digital Signal ◽  
Crumb Rubber ◽  
Granular Systems ◽  
Ottawa Sand ◽  
Dynamic Excitation ◽  
Wave Forms

The characterization and quality assessment of composite materials, particularly those constructed of residual materials such as slags, ashes, and crumb rubber, are difficult because of chemical and physical inhomogeneity and inconsistency at the time of their production. The characterization of granular systems, constructed of a mixture of geological and residual materials, may provide inconclusive information when tested by existing methods. The proposed nondestructive evaluation uses low-strain, low-frequency dynamic excitation as a means to better evaluate such materials. The applied excitation results in a sample response characterized by wave patterns. The wave pattern response is analyzed by digital signal processing and an artificial neural networks (ANN) system to facilitate characterization of the material. Dynamic excitation of representative samples was accomplished using a longitudinal-torsional resonant column. Nondestructive testing was conducted at low strain levels applying a torsional oscillatory motion. The resulting sample response wave forms were recorded. The shear modulus values obtained at the resonant frequency of each sample were used to train an ANN system to characterize sample wave responses measured at random frequencies. The recorded sample response wave forms were analyzed to identify the embedded dominant frequencies, which were unique signatures of the tested materials. These signatures were then submitted to the previously trained ANN to predict the material shear modulus. The samples tested were composed of dry Ottawa sand (0.85 to 0.6 mm), Ottawa sand and crumb rubber modifier, and soda-lime spheres compacted at various densities and tested under different confining pressures. Distinctive patterns, unique to the granular sample composition, were obtained. These are termed the signature patterns. A fast Fourier transform algorithm was used to convert collected data to the frequency domain. ANN analysis was applied to enhance pattern recognition and characterize the samples according to their shear moduli

scholarly journals Design and Implementation of a 32-bit Floating Point Unit

2021 ◽  
Vol 9 (VI) ◽  
pp. 731-736
Author(s):  
Kishan Maladkar
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Digital Signal ◽  
Floating Point ◽  
Verilog Hdl ◽  
Vedic Multiplier ◽  
Common Operation ◽  
Floating Point Unit ◽  
Dsp Processors ◽  
Mathematical Operations

A Floating Point Unit is a math co-processor that is in the most demand of Digital Signal Processing (DSP), Processors and more. It is used to perform functions or operations on floating point numbers like addition, subtraction, multiplication, division, square root and more. It is specifically designed to carry out mathematical operations and it can be emulated in CPU. Floating point unit is a common operation used in advanced Digital Signal Processing and various processor applications. The aim was to develop an optimized floating point unit so that the delay was reduced and efficiency was increased. The floating point unit has been written according to IEEE 754 standard and the entire design has been coded in Verilog HDL. The results are improved by 12% with the usage of Vedic multiplier that is a delay of 4.450ns as compared to 5.123ns with an array multiplier. Designs can be further optimized using low power designing techniques at architectural level. Different behaviour can be observed for different size and technologies.

scholarly journals High speed VLSI Squaring unit of Binary Numbers Design with Yavadunam Sutra and Bit Reduction

2019 ◽  
Vol 9 (2) ◽  
pp. 775-778
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
High Speed ◽  
Digital Signal ◽  
Excellent Performance ◽  
Vedic Mathematics ◽  
Measurement Period

Vedic Mathematics is an ancient Indian algebra in which 16 sutras are used to measure. For excellent performance, most high-speed applications such as cryptography and digital signal processing need powerful and high-speed multipliers. Squaring is a specific case of multiplication. A specialized squaring device can greatly boost the measurement period and significantly reduce the delay. This study discusses the concept of a new square architecture utilizing Vedic-mathematics sutra "Yavadunam." The proposed method uses the amount deficit from the closest base to calculate every operand's circle. The square of a larger number of magnitude is reduced by this method to a smaller multiplication of magnitude and an addition operation

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