scholarly journals Fault-tolerant Structures of Digital Devices Based on Boolean Complement with the Calculations Checking by Sum Codes

2021 ◽  
Vol 43 (5) ◽  
pp. 21-42
Author(s):  
D.V. Efanov ◽  
Keyword(s):  
Error Detection ◽  
Fault Tolerant ◽  
Concurrent Error Detection ◽  
Structural Redundancy ◽  
Computing Systems ◽  
Digital Devices ◽  
Detection Circuit ◽  
Signal Correction ◽  
Modular Redundancy ◽  
Experimental Researches

The article considers the construction of fault-tolerant digital devices and computing systems that does not use the principles of introducing modular redundancy. To correct the signals, a special distorted signal fixation unit, concurrent error-detection by the pre-selected redundant code circuit, as well as a signal correction block are used. The distorted signal fixation unit is implemented by the Boolean complement method, which makes it possible to design a large number of such blocks with different indicators of technical implementation complexity. When synthesizing a fault-tolerant device according to the proposed method, it is possible to organize a concurrent error-detection circuit for both the source device and the Boolean complement block in the structure of the distorted signal fixation unit. This makes it possible to choose among the variety of ways to implement fault-tolerant devices according to the proposed method, one that gives a device with the least structural redundancy. Various redundant codes can be used to organize concurrent error-detection circuits, including classical and modified sum codes. The author provides algorithms for the synthesis of distorted signal fixation unit and the Boolean complement block. The results of experimental researches with combinational benchmarks devices from the well-known LG’91 and MCNC Benchmarks sets are highlighted. The article presents the possibilities of the considered method for the organization of faulttolerant digital devices and computing systems.

Fault Tolerant Techniques for Finite Field Multipliers

2014 ◽  
Vol 573 ◽  
pp. 209-214
Author(s):  
B. Sargunam ◽  
R. Dhanasekaran
Keyword(s):  
Finite Field ◽  
Error Detection ◽  
Fault Tolerant ◽  
High Reliability ◽  
Concurrent Error Detection ◽  
Polynomial Representation ◽  
Finite Field Multiplier ◽  
On Line ◽  
Error Detecting ◽  
Modular Redundancy

The use of finite field multipliers in the critical applications like elliptic curve cryptography needs Concurrent Error Detection (CED) and correction at architectural level to provide high reliability. This paper discusses fault tolerant technique for polynomial representation based finite field multipliers. The detection and correction are done on-line. We use a combination of Double Modular Redundancy (DMR) and Concurrent Error Detection (CED) techniques. The fault tolerant finite field multiplier is coded in VHDL and simulated using Modelsim. Further, the proposed multiplier with fault tolerant capability is synthesized and results are analyzed with respect to area occupied, input and output pin counts and delay. Our technique, when compared with existing techniques, gives better performance. We show that our concurrent error detecting multiplier over GF(2m) requires less than 200% extra hardware, whereas with the traditional fault tolerant techniques, such as Triple Modular Redundancy (TMR), overhead is more than 200%.

Design of an Intelligent Fault-Tolerant System for Real-World Applications

1994 ◽  
Vol 6 (2) ◽  
pp. 150-154
Author(s):  
Shigeki Abe ◽  
◽  
Michitaka Kameyama ◽  
Tatsuo Higuchi ◽  
◽  
...  
Keyword(s):  
Real World ◽  
Error Detection ◽  
Fault Tolerant ◽  
Point Of View ◽  
Fault Tolerant System ◽  
Knowledge Based ◽  
Real World Applications ◽  
Hardware Faults ◽  
Modular Redundancy ◽  
Inference Strategy

To achieve the safety of an intelligent digital system for real-world applications, not only the hardware faults in the processors but also any other faults and errors related to the real world such as sensor faults, actuator faults and human errors must be removed. From this point of view, an intelligent fault-tolerant system for real-world applications is proposed based on triple-modular redundancy. The system consists of a master processor that performs the actual control operations and two redundant processors which simulate real-world process together with the control operations using knowledge-based inference strategy. To realize the independency between the triplicated modules, the simulation for error detection and recovery is performed without actual external sensor signals used in the master processor.

The Concurrent Error-Detection Systems Organization Based on the Boolean Complement Method with the Preliminary Transformation of Operating Functions into Check Vectors of Berger Codes

2021 ◽  
Vol 27 (6) ◽  
pp. 306-313
Author(s):  
D. V. Efanov ◽  
◽  
V. V. Saposhnikov ◽  
Vl. V. Saposhnikov ◽  
◽  
...  
Keyword(s):  
Error Detection ◽  
Concurrent Error Detection ◽  
Structural Redundancy ◽  
Compression Scheme ◽  
Digital Device ◽  
Constant Weight ◽  
Detection Systems ◽  
Detection Characteristics ◽  
Berger Codes

The article describes a new way of concurrent error-detection (CED) systems organization using the Boolean complement method, which involves the use of pre-compression of signals from the diagnostic object using encoders of classical sum codes (Berger codes). Control of compressed signals is carried out using the constant-weight "1-out-of-4" code. In comparison with the known methods of the CED systems organization, it is possible to implement a self-checking digital device using one such circuit, and this significantly reduces the structural redundancy. The article suggests using the encoders of modified Berger codes with improved error detection characteristics as a compression scheme.

scholarly journals Mathematical Modeling and Examination of the Effects of Structural Redundancy in а Class of Computer-Based Fault Tolerant Systems

2016 ◽  
Vol 16 (2) ◽  
pp. 35-45
Author(s):  
Mariya Hristova
Keyword(s):  
Fault Tolerant ◽  
Structural Redundancy ◽  
Mean Time Between Failures ◽  
Reliability Indicators ◽  
Time Between Failures ◽  
Computer Based ◽  
The Mean ◽  
Modular Redundancy ◽  
The Impact ◽  
Mean Time

Abstract The present article models and examines k˅n systems, in particular Triple modular redundancy (2˅3) and 3˅5. The aim of the study is to derive mathematical models, which are used for determining the impact of structural redundancy (the number of channels n and the threshold of the quorum function k) on the reliability of the system. The probability of failure-free operation p and the Mean Time Between Failures (MTBF) are used as reliability indicators.

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