Through-Silicon-Via Copper Deposition for Vertical Chip Integration

ABSTRACTConsumers are demanding smaller, lighter electronic devices with higher performance and more features. The continuous pressure to reduce size, weight, and cost, while increasing the functionality of portable products, has created innovative, cost-effective 3D packaging concepts. Among all kinds of 3D packaging techniques, through-silicon-via (TSV) electrodes can provide vertical connections that are the shortest and most plentiful with several benefits (1). Connection lengths can be as short as the thickness of a chip. High density, high aspect ratio connections are available. TSV interconnections also overcome the RC delays and reduce power consumption by bringing out-of-plane logic blocks much closer electrically.The technologies engaged with TSV chip connection include TSV formation, insulator/barrier/seed deposition, via filling, surface copper removal, wafer thinning, bonding/stacking, inspection, test, etc. Process robustness and speed of copper deposition are among the most important technologies to realize TSV chip integration. There are generally three types of via filling processes; lining along the sidewall of vias, full filling within vias, and full filling with stud formation above the via. Here, the stud works as a mini-bump for solder bonding. Two methodologies have been generally adopted for via filling process; (a) via-first approach : blind-via filling with 3-dimensional seed layer, followed by wafer thinning and (b) thinning-first approach : through-via filling with 2-dimensional seed layer at the wafer bottom after wafer thinning. Currently, the first approach is more popular than the second approach due to difficulty in handling and plating thinned wafers (2).We examined the impact of varying deposition conditions on the overall filling capability within high aspect ratio, deep, blind vias. We tested the impacts of seed layer conformality, surface wettablity, bath composition (organic and inorganic components), waveform (direct current, pulse current, and pulse reverse current), current density, flow conditions, etc. Most deposition conditions affected the filling capability and profile to some extent. We found that reducing current crowding at the via mouth and mass transfer limitation at the via bottom is critical in achieving a super-conformal filling profile. This condition can be only achieved with a proper combination of aforementioned process conditions. With optimized conditions, we can repeatedly achieve void-free, bottom-up filling with various via sizes (5-40μm in width and 25-150μm in depth).