An Approach to Predict 4H-SiC Wafer Bending after Back Side Thinning by Substrate Resistivity Analysis

It is commonly thought that, in the development of SiC power devices with low on-state resistance (Ron), several critical processes in the device fabrication line can strongly impact the final warpage of wafers. High warpage would lead to bad definition of masks, preventing uniform deposition of resist materials and disturbing the normal handling procedures. All these factors would then result in a potential decrease of the electrical yield of the devices, especially for MOSFETs. This study reveals the lack of correlation between critical line processes such as epitaxial growth, oxidations, ion implantations, annealing processes with the final bending of wafers. Conversely, a strong dependence with the resistivity of the substrates is observed. A new parameter defined as RMR (Resistivity Modulation Rate) is taken proposed and, together with the starting value of ingot resistivity, this parameter shows a strong relationship with the final warpage after wafer thinning. A safe region having warpage low enough to allow the workability of the wafers is found.

The Waffle Substrate: A Novel Approach to Reducing Substrate Resistance in SiC Power Devices

Silicon carbide (SiC) is enabling the next generation of semiconductor power devices, with performance orders-of-magnitude beyond silicon. The most important power switching device is the SiC power MOSFET, whose performance is limited by three main resistance elements: the channel, drift layer, and substrate. For blocking voltages in the range of 400-900V, substrate resistance is a major limitation. Wafer thinning is currently used to reduce the substrate resistance, but this also reduces the strength of the wafers. We report on a waffle substrate technique that relies on wafer thinning and inductively coupled plasma (ICP) etching to reduce the substrate resistance below levels achievable by thinning alone, while retaining the mechanical stability of a moderately-thinned substrate. This technique can be applied to any SiC device for which substrate resistance is a limitation.

Reducing On-Resistance for SiC Diodes by Thin Wafer and Laser Anneal Technology

This work presents the influence of Thin Wafer und Laser Anneal Technology on the electrical performance of 4HSiC devices. Substrate thinning and backside ohmic contact formation via laser annealing were successfully applied to in-house designed and manufactured 6 A 650 V SiC diodes at IISB, improving its forward characteristics. The given devices exhibit an on-state voltage drop (VF) reduction from 1.78 V to 1.62 V at 6 A rated current while maintaining blocking capabilities of more than 1.1 kV with leakage currents less than 1 μA at 650 V nominal voltage. On-resistance (RON) was lowered by approx. 30 % to 90 mΩ and 60 % to 12 mΩ in Schottky and conductivity modulation state, respectively. Wafer thinning also allows reducing the influence of non-homogeneous distributed substrate doping concentrations, leading to a more narrow distribution of the forward characteristics of the devices across the wafer.

Etching Rate Profile of C-Face 4H-SiC Wafer Depending on Total Gas Flow Rate of Chlorine Trifluoride and Nitrogen

A 50-mm diameter silicon carbide wafer thinning technique by means of a chemical reaction using a chlorine trifluoride (ClF3) gas was studied accounting for the gas distributor design and the total gas flow rate. The entire etching depth profile could become uniform with the increasing total gas flow rate at the fixed chlorine trifluoride gas concentration. A relationship between the pinhole arrangement of the gas distributor and the local etching rate profile was clarified by comparing the quick calculation and the measurement.