Strontium Bismuth Tantalate Based Ferroelectric Gate Field Effect Transistor with Yttrium Oxide as the Buffer Layer

ABSTRACTWe report the first demonstration of an enhancement mode n-channel metal -ferroelectric-semiconductor field effect transistor (MFISFET) realized directly on silicon with yttrium oxide as the buffer layer. The capacitance-voltage (C-V) characteristics of Metal Ferroelectric Insulator Silicon (MFIS) structures show hysteresis and the direction of hysteresis corresponds to ferroelectric polarization. The memory window in the C-V characteristics was 2V for an applied voltage of ± 10V. The memory window did not show significant change due to decrease in rate of change of sweep voltage and temperature. The transmission electron microscopy (TEM) analysis confirms the formation of an amorphous oxide layer between silicon and yttrium oxide buffer layer.

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Investigation of Protection Layer Materials for Ex-Situ Lift-Out TEM Sample Preparation with FIB for 14 nm FinFET

ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2014p0469 ◽

2014 ◽

Author(s):

H. Feng ◽

G.R. Low ◽

P.K. Tan ◽

Y.Z. Zhao ◽

H.H. Yap ◽

...

Keyword(s):

Electron Microscope ◽

Sample Preparation ◽

Field Effect ◽

Field Effect Transistor ◽

Sample Thickness ◽

Ex Situ ◽

Tem Analysis ◽

Transmission Electron ◽

Protection Layer ◽

Effect Transistor

Abstract With continuous scaling of CMOS device dimensions, sample preparation for Transmission Electron Microscope (TEM) analysis becomes increasingly important and challenging as the required sample thickness is less than several tens of nanometers. This paper studies the protection materials for FIB milling to increase the success rate of ex-situ ‘lift-out’ TEM sample preparation on 14nm Fin-Field Effect Transistor (FinFET).

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Electrical Characteristics of LSMCD-Derived SrBi2.4Ta2O9 Thin Films Using TiO2 Buffer Layer for Metal/Ferroelectric/Insulator/Semiconductor Field Effect Transistor Devices

MRS Proceedings ◽

10.1557/proc-623-31 ◽

2000 ◽

Vol 623 ◽

Author(s):

Joo Dong Park ◽

Tae Sung Oh

Keyword(s):

Thin Films ◽

Buffer Layer ◽

Field Effect ◽

Field Effect Transistor ◽

Chemical Deposition ◽

Memory Window ◽

Buffer Layers ◽

Liquid Source ◽

Effect Transistor ◽

Tio2 Buffer Layer

AbstractPt/SBT/TiO2/Si structure was proposed for metal/ferroelectric/insulator/semiconductor field effect transistor (MFIS-FET) applications. SrBi2.4 Ta2O9 (SBT) thin films of 400 nm thickness were prepared using liquid source misted chemical deposition (LSMCD) on Si(100) substrates with TiO2 buffer layers deposited by DC reactive sputtering with the thickness ranging from 5 nm to 200 nm and electrical properties of MFIS structures were investigated. Memory window and maximum capacitance of the Pt/SBT/TiO2 /Si structure increased with decreasing the thickness of TiO2 buffer layer. The Pt/SBT(400 nm)/TiO2(10 nm)/Si structure exhibited C-V hysteresis loop with the memory window of 1.6 V at ±5 V, and could be applicable for MFISFET applications.

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