Device quantization policy in variation-aware in-memory computing design

Device quantization of in-memory computing (IMC) that considers the non-negligible variation and finite dynamic range of practical memory technology is investigated, aiming for quantitatively co-optimizing system performance on accuracy, power, and area. Architecture- and algorithm-level solutions are taken into consideration. Weight-separate mapping, VGG-like algorithm, multiple cells per weight, and fine-tuning of the classifier layer are effective for suppressing inference accuracy loss due to variation and allow for the lowest possible weight precision to improve area and energy efficiency. Higher priority should be given to developing low-conductance and low-variability memory devices that are essential for energy and area-efficiency IMC whereas low bit precision (< 3b) and memory window (< 10) are less concerned.

Improvement of the Charge Retention of a Non-Volatile Memory by a Bandgap-Engineered Charge Trap Layer

In recent years, research based on HfO2 as a charge trap memory has become increasingly popular. This material, with its advantages of moderate dielectric constant, good interface thermal stability and high charge trap density, is currently gaining in prominence in the next generation of nonvolatile memory devices. In this study, memory devices based on a-IGZO thin-film transistor (TFT) with HfO2/Al2O3/HfO2 charge trap layer (CTL) were fabricated using atomic layer deposition. The effect of the Al2O3 layer thickness (1, 2, and 3 nm) in the CTL on memory performance was studied. The results show that the device with a 2-nm Al2O3 layer in the CTL has a 2.47 V memory window for 12 V programming voltage. The use of the HfO2/Al2O3/HfO2 structure as a CTL lowered the concentration of electrons near the tunnel layer and the loss of trapped electrons. At room temperature, the memory window is expected to decrease by 0.61 V after 10 years. The large storage window (2.47 V) and good charge retention (75.6% in 10 years) of the device under low-voltage conditions are highly advantageous. The charge retention of the HfO2/Al2O3/HfO2 trap layer affords a feasible method for fabricating memory devices based on a-IGZO TFT.

Simulation studies on electrical characteristics of silicon nanowire feedback field-effect transistors with interface trap charges

In this study, we examine the electrical characteristics of silicon nanowire feedback field-effect transistors (FBFETs) with interface trap charges between the channel and gate oxide. The band diagram, I–V characteristics, memory window, and operation were analyzed using a commercial technology computer-aided design simulation. In an n-channel FBFET, the memory window narrows (widens) from 5.47 to 3.59 V (9.24 V), as the density of the positive (negative) trap charges increases. In contrast, in the p-channel FBFET, the memory window widens (narrows) from 5.38 to 7.38 V (4.18 V), as the density of the positive (negative) trap charges increases. Moreover, we investigate the difference in the output drain current based on the interface trap charges during the memory operation.

Electrical Coupling for Monolithic 3-D Integrated Circuit Consisting of Feedback Field-Effect Transistors

In this study, for two cases of monolithic 3-dimensional integrated circuit (M3DIC) consisting of vertically stacked feedback field-effect transistors (FBFETs), the variation of electrical characteristics of the FBFET was presented in terms of electrical coupling by using technology computer aided design (TCAD) simulation. In the Case 1, the M3DIC was composed with an N-type FBFET in an upper tier (tier2) and a P-type FBFET in a lower tier (tier1), and in the Case 2, it was composed with the FBFETs of opposite type of the Case 1 on each tier. To utilize the FBFET as a logic device, the study on optimal structure of FBFET was first performed in terms of reducing a memory window. Based on the N-type FBFET, the memory window was investigated with different values of doping concentration and length of channel region divided into two regions. The threshold voltage, capacitance, and transconductance of two cases of M3DIC composed with proposed FBFET were investigated for different thickness of an interlayer dielectric (TILD). In the Case 1, only for reverse sweep, the threshold voltage of FBFET in the tier2 was changed significantly at TILD < 15 nm, and the capacitance and transconductance of FBFET in the tier2 changed significantly at TILD < 20 nm, as bottom gate voltage applied with 0 and 1 V. In the Case 2, the electrical characteristics of FBFET in the tier2 changed greater than Case 1 with different TILD.