FPGA Implementation of FIR Filter Design Based on Novel Vedic Multiplier

2019 ◽  
Vol 12 (2) ◽  
pp. 66
Author(s):  
Salah H. Alkurwy ◽  
Saad M. Al-Azawi ◽  
Noor A. Al Darraji
Keyword(s):  
Filter Design ◽  
Fir Filter ◽  
Fpga Implementation ◽  
Vedic Multiplier ◽  
Fir Filter Design

scholarly journals FPGA Implementation of Efficient FIR Filter

2020 ◽  
Vol 9 (3) ◽  
pp. 3410-3412
Keyword(s):  
Programming Language ◽  
Filter Design ◽  
Fir Filter ◽  
Fpga Implementation ◽  
Floating Point ◽  
Matlab Software ◽  
Dynamic Power ◽  
Main Target ◽  
Filter Operation ◽  
Fir Filter Design

Improve the functionality of an FIR Filter by modifying the internal components used to design a filter. These past years have seen some great improvements in the speed, power, and area of the filter. Here, we will, therefore, use an ALU-based algorithm to design our FIR filter. The internal components of the ALU block will be an Adder and a Multiplier. A Floating point Adder and a Floating Point Multiplier will be the basic backbone of the ALU block, which finally will be used to design and implement our FIR filter design. Therefore, the parameters of the area are our main target but we will also see the power consumed by the Filter operation, both static and dynamic power consumed will be seen. The programming language will be written in VERILOG and the simulation and implementation of the design will be done by the help of Xilinx ISE suite version. One important aspect is that there will be 16 input samples and 16 coefficients which will be directly from a 16 tap filter. These coefficients and input values will be generated through MATLAB software.

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