A -104dBc/Hz In-Band Phase Noise 3GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter

2012 ◽  
Vol E95.C (6) ◽  
pp. 1008-1016 ◽  
Author(s):  
Daisuke MIYASHITA ◽  
Hiroyuki KOBAYASHI ◽  
Jun DEGUCHI ◽  
Shouhei KOUSAI ◽  
Mototsugu HAMADA ◽  
...  
Author(s):  
Khalil Gammoh ◽  
Cameron K. Peterson ◽  
David Aaron Penry ◽  
Shiuh-Hua Wood Chiang

2010 ◽  
Vol 45 (12) ◽  
pp. 2582-2590 ◽  
Author(s):  
Takashi Tokairin ◽  
Mitsuji Okada ◽  
Masaki Kitsunezuka ◽  
Tadashi Maeda ◽  
Muneo Fukaishi

2016 ◽  
Vol 25 (11) ◽  
pp. 1650131
Author(s):  
Sungkyung Park ◽  
Chester Sungchung Park

All-digital phase-locked loops (ADPLLs) based on the time-to-digital converter (TDC) and the frequency discriminator (FD) are modeled and analyzed in terms of quantization effects. Using linear models with quantization noise sources, theoretical analysis and simulation are carried out to obtain the output phase noise of each building block of the TDC-based ADPLL. It is newly derived that the TDC noise component caused by the delta-sigma modulator (DSM) and the finite resolution of the digitally controlled oscillator is not white. Namely, the in-band phase noise caused by the DSM-induced TDC is not white, which is due to the integrate-and-dump and subsampling operations of the TDC. This can give some insight into the design of low-noise ADPLLs. Some structures of delta-sigma FDs, which can serve as an alternative to the TDC, are also newly analyzed in terms of quantization noise, using the derived linear noise model.


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