scholarly journals Control neuronal de un sistema de equilibrio (péndulo invertido) en dispositivos lógicos programables

2017 ◽  
Vol 4 (2) ◽  
pp. 40
Author(s):  
Johnny Omar Medina Durán ◽  
Norbey Chinchilla Herrera ◽  
Ruby Daniela Vargas Quintero ◽  
Yesenia Restrepo Chaustre

Este trabajo presenta la implementación de una Red Neuronal FeedFoward para el control de equilibrio de un sistema sobre dos ruedas (péndulo invertido), en una tarjeta de desarrollo Nexys 2 de Digilent, que contiene una FPGA (Field Programmable Gate Array) XC3S500E. La herramienta utilizada para la creación, entrenamiento y simulación de la red neuronal fue la NNTool de Matlab. El algoritmo neuronal fue traducido a un modelo realizable en hardware, mediante diagramas de bloques, desarrollados con las herramientas Simulink y Xilinx System Generator (XSG). La validación de la red neuronal se realiza en un prototipo de equilibrio sobre dos ruedas. Este sistema tiene una unidad de medida inercial (IMU 6dof- MPU 6050), que incluyen un acelerómetro y un giroscopio de tres ejes cada uno, y 2 motorreductores con encoder magnético, utilizados como actuadores.

2008 ◽  
Author(s):  
Michael Wirthlin ◽  
Brent Nelson ◽  
Brad Hutchings ◽  
Peter Athanas ◽  
Shawn Bohner

2020 ◽  
Vol 91 (10) ◽  
pp. 104707
Author(s):  
Yinyu Liu ◽  
Hao Xiong ◽  
Chunhui Dong ◽  
Chaoyang Zhao ◽  
Quanfeng Zhou ◽  
...  

2021 ◽  
Vol 11 (8) ◽  
pp. 3330
Author(s):  
Pietro Nannipieri ◽  
Stefano Di Matteo ◽  
Luca Baldanzi ◽  
Luca Crocetti ◽  
Jacopo Belli ◽  
...  

Random numbers are widely employed in cryptography and security applications. If the generation process is weak, the whole chain of security can be compromised: these weaknesses could be exploited by an attacker to retrieve the information, breaking even the most robust implementation of a cipher. Due to their intrinsic close relationship with analogue parameters of the circuit, True Random Number Generators are usually tailored on specific silicon technology and are not easily scalable on programmable hardware, without affecting their entropy. On the other hand, programmable hardware and programmable System on Chip are gaining large adoption rate, also in security critical application, where high quality random number generation is mandatory. The work presented herein describes the design and the validation of a digital True Random Number Generator for cryptographically secure applications on Field Programmable Gate Array. After a preliminary study of literature and standards specifying requirements for random number generation, the design flow is illustrated, from specifications definition to the synthesis phase. Several solutions have been studied to assess their performances on a Field Programmable Gate Array device, with the aim to select the highest performance architecture. The proposed designs have been tested and validated, employing official test suites released by NIST standardization body, assessing the independence from the place and route and the randomness degree of the generated output. An architecture derived from the Fibonacci-Galois Ring Oscillator has been selected and synthesized on Intel Stratix IV, supporting throughput up to 400 Mbps. The achieved entropy in the best configuration is greater than 0.995.


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