SOFTWARE-DEFINED RADAR TARGET SIMULATOR WITH DRFM FOR AUTOMATED RADARS TESTING

The paper describes a software-defined radar target simulator with DRFM. One may use such a device to test radars under development and evaluate their reliability in environments with radio frequency interference. The paper describes in detail a general algorithm of the target simulation and its modules for the simulation of range and speed. The authors also implemented the frequency shift module for the simulator in Xilinx System Generator and wrote this module in VHDL. One may find in the paper a comparison of the FPGA resources required for such implementations.

A Guide on Using Xilinx System Generator to Design and Implement Real-Time Audio Effects on FPGA

The enormous progress in communication technology has led to a tremendous need to provide an ideal environment for the transmission, storing, and processing of digital multimedia content, where the audio signal takes the lion's share of it. Audio processing covers many diverse fields, its main aim is presenting sound to human listeners. Recently, digital audio processing became an active research area, it covers everything from theory to practice in relation to transmission, compression, filtering, and adding special effects to an audio signal. The aim of this work is to present the real-time implementation steps of some audio effects namely, the echo and Flanger effects on Field Programmable Gate Array (FPGA). Today, FPGAs are the best choice in data processing because they provide more flexibility, performance, and huge processing capabilities with great power efficiency. Designs are achieved using the XSG tool (Xilinx System Generator), which makes complex designs easier without prior knowledge of hardware description languages. The paper is presented as a guide with deep technical details about designing and real-time implementation steps. We decided to transfer some experience to designers who want to rapidly prototype their ideas using tools such as XSG. All the designs have been simulated and verified under Simulink/Matlab environment, then exported to Xilinx ISE (Integrated Synthesis Environment) tool for the rest of the implementation steps. The paper also gives an idea of interfacing the FPGA with the LM4550 AC’97 codec using VHDL coding. The ATLYS development board based on Xilinx Spartan-6 LX45 FPGA is used for the real-time implementation.

Co-simulation of linear congruential generator by using Xilinx system generator and MATLAB Simulink

<p>Arbitrary numerals are utilized in a wide range of uses. Genuine arbitrary numeral generators are moderate and costly for some applications while pseudo arbitrary numeral generators (RNG) do the trick for most applications. This paper fundamentally concentrates around the co-simulation of the linear congruential generator (LCG) model utilizing the Xilinx System generator and checking on Matlab Simulink. The design is obtained from the LCG calculation offered by Lehmer. Word lengths decrease strategy has been utilized to streamline the circuit. Simulation has been done effectively. The effective N bit LCG is structured and tried by utilizing demonstrating in MatLab Simulink. The Co-simulation of the model is done by utilizing the Xilinx system generator. This paper conducts an exhaustive search for the best arbitrary numeral generator in a full period linear congruential generator (LCG) with the largest prime numbers.</p>