scholarly journals Design and Implementation of High Speed and Low Power Modified Square Root Carry Select Adder (MSQRTCSLA)

2016 ◽  
Vol 12 (1) ◽  
pp. 43-51
Author(s):  
C. Uthayakumar ◽  
B. Justus Rabi
Keyword(s):  
Low Power ◽  
High Speed ◽  
Square Root ◽  
Design And Implementation ◽  
Carry Select Adder

Design and Implementation of High-Speed Low-Power Carry Select Adder

2021 ◽  
pp. 517-530
Author(s):  
Kummetha Deepthi ◽  
Pratheeksha Bhaskar ◽  
M. Priyanka ◽  
B. V. Sonika ◽  
B. N. Shashikala
Keyword(s):  
Low Power ◽  
High Speed ◽  
Design And Implementation ◽  
Carry Select Adder

scholarly journals Low power add-one circuit IPGL based high speed square root carry select adder

2021 ◽  
Vol 14 (9) ◽  
pp. 776-786
Author(s):  
B S Premananda ◽  
◽  
Archit Bajpai ◽  
G Shakthivel ◽  
A R Anurag
Keyword(s):  
Low Power ◽  
High Speed ◽  
Square Root ◽  
Carry Select Adder

Proposed low power, high speed adder-based 65-nm Square root circuit

2011 ◽  
Vol 42 (2) ◽  
pp. 445-451 ◽  
Author(s):  
C. Senthilpari ◽  
Zuraida Irina Mohamad ◽  
S. Kavitha
Keyword(s):  
Low Power ◽  
High Speed ◽  
Square Root

Low Power and High Speed Dadda Multiplier using Carry Select Adder with Binary to Excess-1 Converter

2020 ◽  
Author(s):  
Muteen Munawar ◽  
Talha Khan ◽  
Muhammad Rehman ◽  
Zain Shabbir ◽  
Kamran Daniel ◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Carry Select Adder

scholarly journals FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders

2015 ◽  
Vol 2015 ◽  
pp. 1-13 ◽  
Author(s):  
V. Kokilavani ◽  
K. Preethi ◽  
P. Balasubramanian
Keyword(s):  
High Speed ◽  
Boolean Logic ◽  
The Other ◽  
Square Root ◽  
Verilog Hdl ◽  
Other Hand ◽  
Carry Select Adder

Carry select adder is a square-root time high-speed adder. In this paper, FPGA-based synthesis of conventional and hybrid carry select adders are described with a focus on high speed. Conventionally, carry select adders are realized using the following: (i) full adders and 2 : 1 multiplexers, (ii) full adders, binary to excess 1 code converters, and 2 : 1 multiplexers, and (iii) sharing of common Boolean logic. On the other hand, hybrid carry select adders involve a combination of carry select and carry lookahead adders with/without the use of binary to excess 1 code converters. In this work, two new hybrid carry select adders are proposed involving the carry select and section-carry based carry lookahead subadders with/without binary to excess 1 converters. Seven different carry select adders were implemented in Verilog HDL and their performances were analyzed under two scenarios, dual-operand addition and multioperand addition, where individual operands are of sizes 32 and 64-bits. In the case of dual-operand additions, the hybrid carry select adder comprising the proposed carry select and section-carry based carry lookahead configurations is the fastest. With respect to multioperand additions, the hybrid carry select adder containing the carry select and conventional carry lookahead or section-carry based carry lookahead structures produce similar optimized performance.

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