FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders

Carry select adder is a square-root time high-speed adder. In this paper, FPGA-based synthesis of conventional and hybrid carry select adders are described with a focus on high speed. Conventionally, carry select adders are realized using the following: (i) full adders and 2 : 1 multiplexers, (ii) full adders, binary to excess 1 code converters, and 2 : 1 multiplexers, and (iii) sharing of common Boolean logic. On the other hand, hybrid carry select adders involve a combination of carry select and carry lookahead adders with/without the use of binary to excess 1 code converters. In this work, two new hybrid carry select adders are proposed involving the carry select and section-carry based carry lookahead subadders with/without binary to excess 1 converters. Seven different carry select adders were implemented in Verilog HDL and their performances were analyzed under two scenarios, dual-operand addition and multioperand addition, where individual operands are of sizes 32 and 64-bits. In the case of dual-operand additions, the hybrid carry select adder comprising the proposed carry select and section-carry based carry lookahead configurations is the fastest. With respect to multioperand additions, the hybrid carry select adder containing the carry select and conventional carry lookahead or section-carry based carry lookahead structures produce similar optimized performance.

Reconfigurable CPLAG and Modified PFAL Adiabatic Logic Circuits

Previously, authors have proposed CPLAG and MCPLAG circuits extracting benefits of CPL family implemented based upon semiadiabatic logic for low power VLSI circuit design along with gating concept. Also authors have communicated RCPLAG circuits adding another dimension of reconfigurability into CPLAG/MCPLAG circuits. Moving ahead, in this paper, authors have implemented/reconfigured RCPLAG universal Nand/And gate and universal Nor/Or gate for extracting behavior of dynamic positive edge triggered DFF. Authors have also implemented Adder/Subtractor circuit using different techniques. Authors have also reported modification in PFAL semiadiabatic circuit family to further reduce the power dissipation. Functionality of these is verified and found to be satisfactory. Further these are examined rigorously with voltage, Cload, temperature, and transistor size variation. Performance of these is examined with these variations with power dissipation, delays, rise, and fall times associated. From the analysis it is found that best operating condition for DFF based upon RCPLAG universal gate can be achieved at supply voltage lower than 3 V which can be used for different transistor size up to 36 μm. Average power dissipation is 0.2 μW at 1 V and 30 μW at 2 V at 100 ff Cload 25°C approximately. Average power dissipated by CPLAG Adder/Subtractot is 58 μW. Modified PFAL circuit reduces average power by 9% approximately.

High Efficiency Driver for AMOLED with Compensation

A new proposed compensation driver circuit of flat-panel display (FPD) based on organic light emitting diodes (OLEDs) and on poly-crystalline silicon thin-film transistors (poly-Si TFTs) is presented. This driver circuit is developed for an active-matrix organic light-emitting-diode (AMOLED) display and its efficiency is verified compared with the conventional configuration with 2 TFTs. According to results, this circuit is suitable to achieve acceptable level for power consumption, high contrast, maximum gray levels, and better brightness. And, to show this, a stable driving scheme is developed for circuit with much compensation such as against the data degradation, the threshold voltage dispersions of TFT drive, and suppression of TFT leakage current effect.

All Pass Network Based MSO Using OTRA

This paper presents multiphase sinusoidal oscillators (MSOs) using operational transresistance amplifier (OTRA) based all pass networks. Both even and odd phase oscillations of equal amplitudes which are equally spaced in phase can be produced using single all pass section per phase. The proposed MSOs provide voltage output and can readily be used for driving voltage input circuits without increasing component count. The effect of nonideality of OTRA on the circuit performance is also analysed. The functionality of the proposed circuit is verified through PSPICE simulations.

Design and Implementation of Android Based Wearable Smart Locator Band for People with Autism, Dementia, and Alzheimer

A wearable smart locator band is an electronic device which can be worn on the wrist of the children to monitor and keep an eye on them. As the number of mishaps with children is increasing, it is a must to keep them safe. This also helps reducing crime rates. The research study proposed the development of a wearable smart locator band that helps keeping track of kids. The developed device includes an AVR microcontroller (ATmega8515), global positioning system (GPS), global system for mobile (GSM), and switching unit and the monitoring unit includes Android mobile device in parent’s hand with web based Android application as well as location indicated on a Google Map. This development is very useful for senior people and individuals suffering from memory diseases. This device, hence, behaves as a communication interface between wearer and caregiver.

Blood Glucose Measurement Using Bioimpedance Technique

Bioimpedance measurement is gaining importance in wide field of bioresearch and biomedical systems due to its noninvasive nature. Noninvasive measurement method is very important to decrease infection and physical injuries which result due to invasive measurement. This paper presents basic principle of bioimpedance along with its application for blood glucose analysis and effect of frequency on impedance measurement. Input from bioimpedance sensor is given to amplifier and signal conditioner AD5933. AD5933 is then interfaced with microcontroller LPC1768 using I2C bus for displaying reading on LCD. Results can also be stored in database using UART interface of LPC1768.

Design of CDTA and VDTA Based Frequency Agile Filters

This paper presents frequency agile filters based on current difference transconductance amplifier (CDTA) and voltage difference transconductance amplifier (VDTA). The proposed agile filter configurations employ grounded passive components and hence are suitable for integration. Extensive SPICE simulations using 0.25 μm TSMC CMOS technology model parameters are carried out for functional verification. The proposed configurations are compared in terms of performance parameters such as power dissipation, signal to noise ratio (SNR), and maximum output noise voltage.

Low Power Data Acquisition System for Bioimplantable Devices

Signal acquisition represents the most important block in biomedical devices, because of its responsibilities to retrieve precise data from the biological tissues. In this paper an energy efficient data acquisition unit is presented which includes low power high bandwidth front-end amplifier and a 10-bit fully differential successive approximation ADC. The proposed system is designed with 0.18 µm CMOS technology and the simulation results show that the bioamplifier maintains a wide bandwidth versus low noise trade-off and the proposed SAR-ADC consumes 450 nW power under 1.8 V supply and retain the effective number of bit 9.55 in 100 KS/s sampling rate.

Shifting the Frontiers of Analog and Mixed-Signal Electronics

Nowadays, analog and mixed-signal (AMS) IC designs, mainly found in the frontends of large ICs, are highly dedicated, complex, and costly. They form a bottleneck in the communication with the outside world, determine an upper bound in quality, yield, and flexibility for the IC, and require a significant part of the power dissipation. Operating very close to physical limits, serious boundaries are faced. This paper relates, from a high-level point of view, these boundaries to the Shannon channel capacity and shows how the AMS circuitry forms a matching link in transforming the external analog signals, optimized for the communication medium, to the optimal on-chip signal representation, the digital one, for the IC medium. The signals in the AMS part itself are consequently not optimally matched to the IC medium. To further shift the frontiers of AMS design, a matching-driven design approach is crucial for AMS. Four levels will be addressed: technology-driven, states-driven, redundancy-driven, and nature-driven design. This is done based on an analysis of the various classes of AMS signals and their specific properties, seen from the angle of redundancy. This generic, but abstract way of looking at the design process will be substantiated with many specific examples.