Design and Implementation of 3-bit Flash Analog to Digital Converter for Low Power and High Speed Applications with New Ex-OR Based ROM Encoder

2021 ◽  
pp. 613-626
Author(s):  
S. S. Kamate ◽  
H. P. Rajani
Keyword(s):  
Low Power ◽  
High Speed ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Design And Implementation

scholarly journals A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor

2017 ◽  
Vol 2017 ◽  
pp. 1-15 ◽  
Author(s):  
Mostafa Chakir ◽  
Hicham Akhamal ◽  
Hassan Qjidaa
Keyword(s):  
Low Power ◽  
Input Signal ◽  
Small Area ◽  
High Speed ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Active Pixel Sensor ◽  
Analog To Digital ◽  
Active Pixel ◽  
5 Ghz

The CMOS Monolithic Active Pixel Sensor (MAPS) for the International Linear Collider (ILC) vertex detector (VXD) expresses stringent requirements on their analog readout electronics, specifically on the analog-to-digital converter (ADC). This paper concerns designing and optimizing a new architecture of a low power, high speed, and small-area 4-bit column-parallel ADC Flash. Later in this study, we propose to interpose an S/H block in the converter. This integration of S/H block increases the sensitiveness of the converter to the very small amplitude of the input signal from the sensor and provides a sufficient time to the converter to be able to code the input signal. This ADC is developed in 0.18 μm CMOS process with a pixel pitch of 35 μm. The proposed ADC responds to the constraints of power dissipation, size, and speed for the MAPS composed of a matrix of 64 rows and 48 columns where each column ADC covers a small area of 35 × 336.76 μm2. The proposed ADC consumes low power at a 1.8 V supply and 100 MS/s sampling rate with dynamic range of 125 mV. Its DNL and INL are 0.0812/−0.0787 LSB and 0.0811/−0.0787 LSB, respectively. Furthermore, this ADC achieves a high speed more than 5 GHz.

scholarly journals Design & Implementation of Low Power 3-bit Flash ADC in 0.18μm CMOS

2012 ◽  
pp. 89-93
Author(s):  
Pradeep Kumar ◽  
Amit Kolhe
Keyword(s):  
Power Consumption ◽  
Response Time ◽  
Low Power ◽  
Cmos Technology ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Chip Area ◽  
Flash Adc ◽  
Analog To Digital ◽  
Design And Implementation

This paper describes the design and implementation of a Low Power 3-bit flash Analog to Digital converter (ADC). It includes 7 comparators and one thermometer to binary encoder. It is implemented in 0.18um CMOS Technology. The presimulation of ADC is done in T-Spice and post layout simulation is done in Microwind3.1. The response time of the comparator equal to 6.82ns and for Flash ADC as 18.77ns.The Simulated result shoes the power consumption in Flash ADC as is 36.273mw .The chip area is for Flash ADC is 1044um2 .

Design of a High Speed and Low Power Analog to Digital Converter

2017 ◽  
Vol 14 (3) ◽  
pp. 1521-1523
Author(s):  
P. Venugopal ◽  
V. Ranganathan ◽  
N. Ramadass
Keyword(s):  
Low Power ◽  
High Speed ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital
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