scholarly journals The Method of the Concurrent Error-detection of Combinational Logic Devices Based on the Self-dual Complement to Constant-weight Code

2020 ◽  
Vol 42 (3) ◽  
pp. 27-52
Author(s):  
D.V. Efanov ◽  
◽  
V.V. Sapozhnikov ◽  
Vl.V Sapozhnikov ◽  
D.V. Pivovarov ◽  
...  
2021 ◽  
pp. 81-94
Author(s):  
D.V. Efanov ◽  
◽  
D.V. Pivovarov ◽  

A method for self-checking concurrent error-detection circuit synthesis based on Boolean com-plement and "2-out-of-5" constant-weight code is described. The method is notable for using functional relationship between the signals from the working and control outputs instead of ana-lyzing the unit performance on each input. The functional dependence is established with due account to the requirements for the formation of codewords of the "2-out-of-5" code and a com-plete tester check. In addition, it considers the formation of a complete set of test combinations for transformation elements in the concurrent error-detection circuit. A method for obtaining a functional relationship between the control outputs and the operating outputs of the diagnostic object is presented. One of the options for extending the definition of the control function values is presented, as well as the functional dependence. It is noted that the number of options for ex-tending the definition of the control function values is large, which allows numerous options for synthesizing a concurrent error-detection circuit for any diagnostic object based on the described method. The use of the "2-out-of-5" code for the synthesis of concurrent error-detection circuits applying the Boolean complement method proved its effectiveness for organizing self-checking digital devices in automatics and computer technology.


2004 ◽  
Vol 17 (1) ◽  
pp. 69-79
Author(s):  
Tatjana Stankovic ◽  
Mile Stojcev ◽  
Goran Djordjevic

Concurrent error detection (CED) is an important technique in the design of system in which dependability and data integrity are important. Using the separable code for CED has the advantage that no decoding is needed to get the normal output bits. In this paper, we address the problem of synthesizing totally self-checking two level combinational circuits starting from a VHDL description. Three schemes for CED are proposed. The first scheme uses duplication of a combinational logic with the addition of a totally self-checking comparator. The second scheme for synthesizing combinational circuits with CED uses Bose-Lin code. The third scheme is based on parity codes on the outputs of a combinational circuit. The area overheads and operating speed decreases for seven combinational circuits of standard architecture are reported in this paper.


2021 ◽  
Vol 27 (6) ◽  
pp. 306-313
Author(s):  
D. V. Efanov ◽  
◽  
V. V. Saposhnikov ◽  
Vl. V. Saposhnikov ◽  
◽  
...  

The article describes a new way of concurrent error-detection (CED) systems organization using the Boolean complement method, which involves the use of pre-compression of signals from the diagnostic object using encoders of classical sum codes (Berger codes). Control of compressed signals is carried out using the constant-weight "1-out-of-4" code. In comparison with the known methods of the CED systems organization, it is possible to implement a self-checking digital device using one such circuit, and this significantly reduces the structural redundancy. The article suggests using the encoders of modified Berger codes with improved error detection characteristics as a compression scheme.


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