scholarly journals AREA EFFICIENT AND HIGH SPEED ALU USING 64 BIT MODIFIED SQUARE ROOT CARRY SELECT ADDER

2017 ◽  
Vol 58 ◽  
pp. 101-112 ◽  
Author(s):  
Milad Bahadori ◽  
Mehdi Kamal ◽  
Ali Afzali-Kusha ◽  
Massoud Pedram

2015 ◽  
Vol 2015 ◽  
pp. 1-13 ◽  
Author(s):  
V. Kokilavani ◽  
K. Preethi ◽  
P. Balasubramanian

Carry select adder is a square-root time high-speed adder. In this paper, FPGA-based synthesis of conventional and hybrid carry select adders are described with a focus on high speed. Conventionally, carry select adders are realized using the following: (i) full adders and 2 : 1 multiplexers, (ii) full adders, binary to excess 1 code converters, and 2 : 1 multiplexers, and (iii) sharing of common Boolean logic. On the other hand, hybrid carry select adders involve a combination of carry select and carry lookahead adders with/without the use of binary to excess 1 code converters. In this work, two new hybrid carry select adders are proposed involving the carry select and section-carry based carry lookahead subadders with/without binary to excess 1 converters. Seven different carry select adders were implemented in Verilog HDL and their performances were analyzed under two scenarios, dual-operand addition and multioperand addition, where individual operands are of sizes 32 and 64-bits. In the case of dual-operand additions, the hybrid carry select adder comprising the proposed carry select and section-carry based carry lookahead configurations is the fastest. With respect to multioperand additions, the hybrid carry select adder containing the carry select and conventional carry lookahead or section-carry based carry lookahead structures produce similar optimized performance.


2016 ◽  
Vol 89 ◽  
pp. 640-650 ◽  
Author(s):  
Bala Sindhuri Kandula ◽  
K. Padma Vasavi ◽  
I. Santi Prabha

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1129
Author(s):  
You ◽  
Yuan ◽  
Tang ◽  
Qiao

In this paper, an energy and area efficient carry select adder (CSLA) is proposed. To minimize the redundant logic operation of a regular CSLA, a dual carry adder cell is proposed. The proposed dual carry adder is composed of an XOR/XNOR cell and two pairs of sum-carry cells. Both CMOS logic and a transmission gate were applied to the dual carry adder cell to achieve fast and energy efficient operation. Eight-bit, 16b, and 32b square-root (SQRT) CSLAs based on the proposed dual carry adder were developed. The post-layout simulation based on a SMIC 55 nm process demonstrated that the proposed CSLAs reduced power consumption by 68.4–72.2% with a slight delay increase for different bit widths. As the dual carry adder had much fewer transistors than the two regular full adders, the area of the proposed CSLAs was reduced by 45.8–51.1%. The area-power-delay product of the proposed CSLA improved 5.1×–6.73× compared with the regular CSLA.


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