Multiple Error Recovery in FIR Filter using Reduced-Precision Redundancy (RPR)

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

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Design of digital FIR filter using dynamic distributed arithmetic algorithm with improved table look up scheme for residue number system

IET-UK International Conference on Information and Communication Technology in Electrical Sciences (ICTES 2007) ◽

10.1049/ic:20070683 ◽

2007 ◽

Author(s):

T. Vigneswaran ◽

J. Selva Kumar ◽

P. Subbarami Reddy

Keyword(s):

Number System ◽

Residue Number System ◽

Fir Filter ◽

Distributed Arithmetic ◽

Residue Number ◽

Arithmetic Algorithm

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Efficient Estimation of CFO-Affected OFDM BER Floor in Small Cells with Resource-Limited IoT End-Points

Sensors ◽

10.3390/s20133747 ◽

2020 ◽

Vol 20 (13) ◽

pp. 3747

Author(s):

Adriana Lipovac ◽

Vlatko Lipovac ◽

Borivoj Modlic

Keyword(s):

Orthogonal Frequency Division Multiplexing ◽

Carrier Frequency Offset ◽

Signal To Noise Ratio ◽

Low Cost ◽

Error Recovery ◽

Efficient Estimation ◽

Analytical Models ◽

Small Cells ◽

End Points ◽

Power Delay Profile

Contemporary wireless networks dramatically enhance data rates and latency to become a key enabler of massive communication among various low-cost devices of limited computational power, standardized by the Long-Term Evolution (LTE) downscaled derivations LTE-M or narrowband Internet of Things (NB IoT), in particular. Specifically, assessment of the physical-layer transmission performance is important for higher-layer protocols determining the extent of the potential error recovery escalation upwards the protocol stack. Thereby, it is needed that the end-points of low processing capacity most efficiently estimate the residual bit error rate (BER) solely determined by the main orthogonal frequency-division multiplexing (OFDM) impairment–carrier frequency offset (CFO), specifically in small cells, where the signal-to-noise ratio is large enough, as well as the OFDM symbol cyclic prefix, preventing inter-symbol interference. However, in contrast to earlier analytical models with computationally demanding estimation of BER from the phase deviation caused by CFO, in this paper, after identifying the optimal sample instant in a power delay profile, we abstract the CFO by equivalent time dispersion (i.e., by additional spreading of the power delay profile that would produce the same BER degradation as the CFO). The proposed BER estimation is verified by means of the industry-standard LTE software simulator.

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