Low Area FPGA Implementation of SP-box PRESENT Cryptography with MSCLCG Key Generation

Chaotic systems plays a vital role in the field of security, data hiding and steganography. FPGA implementation makes more advantageous compared to analog one. Different chaotic systems like chaos generator and nondeterministic number generator used for security purpose and key generation were successfully realized in FPGA. In this paper, FPGA implementation of Pandey-Baghel-Singh chaotic system (PBSCS) using Euler and RK4 numerical algorithms is presented. Pandey-Baghel-Singh chaotic system were obtained using numerical differential solution and numerically modelled in Verilog with the environment of Xilinx Vivado 2017.3 design suite. The design is verified using experimental setup with the help of interfacing to PC and FPGA family of Artix-7 Nexys 4 DDR and Basys3. Performance of the FPGA based chaotic generator using Euler and RK4 algorithm are analyzed using 1 GB data sets with the maximum operating frequency achieved up to 359.71 MH

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Low-Cost, Low-Power FPGA Implementation of ED25519 and CURVE25519 Point Multiplication

Information ◽

10.3390/info10090285 ◽

2019 ◽

Vol 10 (9) ◽

pp. 285 ◽

Cited By ~ 1

Author(s):

Mohamad Ali Mehrabi ◽

Christophe Doche

Keyword(s):

Low Power ◽

Low Cost ◽

Fpga Implementation ◽

Large Integer ◽

Modular Multiplication ◽

Point Multiplication ◽

Low Area ◽

Edwards Curves ◽

Digital Signature Algorithm ◽

Edwards Curve

Twisted Edwards curves have been at the center of attention since their introduction by Bernstein et al. in 2007. The curve ED25519, used for Edwards-curve Digital Signature Algorithm (EdDSA), provides faster digital signatures than existing schemes without sacrificing security. The CURVE25519 is a Montgomery curve that is closely related to ED25519. It provides a simple, constant time, and fast point multiplication, which is used by the key exchange protocol X25519. Software implementations of EdDSA and X25519 are used in many web-based PC and Mobile applications. In this paper, we introduce a low-power, low-area FPGA implementation of the ED25519 and CURVE25519 scalar multiplication that is particularly relevant for Internet of Things (IoT) applications. The efficiency of the arithmetic modulo the prime number 2 255 - 19 , in particular the modular reduction and modular multiplication, are key to the efficiency of both EdDSA and X25519. To reduce the complexity of the hardware implementation, we propose a high-radix interleaved modular multiplication algorithm. One benefit of this architecture is to avoid the use of large-integer multipliers relying on FPGA DSP modules.

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