Universal quantum computation with quantum-dot cellular automata in decoherence-free subspace

2008 ◽  
Vol 8 (10) ◽  
pp. 977-985
Author(s):  
Z.-Y. Xu ◽  
M. Feng ◽  
W.-M. Zhang
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Quantum Computation ◽  
Two Dimensions ◽  
High Fidelity ◽  
Electron Pairs ◽  
Quantum Dot Cellular Automata ◽  
Single Spin ◽  
Universal Quantum ◽  
Decoherence Free Subspace

We investigate the possibility to have electron-pairs in decoherence-free subspace (DFS), by means of the quantum-dot cellular automata (QCA) and single-spin rotations, to deterministically carry out a universal quantum computation with high-fidelity. We show that our QCA device with electrons tunneling in two dimensions is very suitable for DFS encoding, and argue that our design favors a scalable quantum computation robust to collective dephasing errors.

QUANTUM COMPUTATION BASED ON ELECTRON SPIN QUBITS WITHOUT SPIN-SPIN INTERACTION

2005 ◽  
Vol 03 (supp01) ◽  
pp. 155-162
Author(s):  
YIN-ZHONG WU ◽  
WEI-MIN ZHANG ◽  
CHOPIN SOO
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Quantum Computation ◽  
Electron Spin ◽  
Electron Tunneling ◽  
Entangled State ◽  
Spin Interaction ◽  
Quantum Dot Cellular Automata ◽  
Universal Quantum ◽  
Coherent Quantum

Using electron spin states in a unit cell of three semiconductor quantum dots as qubit states, a scalable quantum computation scheme is advocated without invoking qubit-qubit interactions. Single electron tunneling technology and coherent quantum-dot cellular automata architecture are used to generate an ancillary charge entangled state which is then converted into spin entangled state. Without using charge measurement and ancillary qubits, we demonstrate universal quantum computation based on free electron spin and coherent quantum-dot cellular automata.

scholarly journals Two-qubit sweet spots for capacitively coupled exchange-only spin qubits

2021 ◽  
Vol 7 (1) ◽  
Author(s):  
MengKe Feng ◽  
Lin Htoo Zaw ◽  
Teck Seng Koh
Keyword(s):  
Quantum Dot ◽  
Quantum Computation ◽  
Parameter Space ◽  
Capacitive Coupling ◽  
High Fidelity ◽  
Spin Qubits ◽  
Capacitively Coupled ◽  
Universal Quantum ◽  
Qubit Gate ◽  
Sweet Spots

AbstractThe implementation of high fidelity two-qubit gates is a bottleneck in the progress toward universal quantum computation in semiconductor quantum dot qubits. We study capacitive coupling between two triple quantum dot spin qubits encoded in the S = 1/2, Sz = −1/2 decoherence-free subspace—the exchange-only (EO) spin qubits. We report exact gate sequences for CPHASE and CNOT gates, and demonstrate theoretically, the existence of multiple two-qubit sweet spots (2QSS) in the parameter space of capacitively coupled EO qubits. Gate operations have the advantage of being all-electrical, but charge noise that couple to electrical parameters of the qubits cause decoherence. Assuming noise with a 1/f spectrum, two-qubit gate fidelities and times are calculated, which provide useful information on the noise threshold necessary for fault-tolerance. We study two-qubit gates at single and multiple parameter 2QSS. In particular, for two existing EO implementations—the resonant exchange (RX) and the always-on exchange-only (AEON) qubits—we compare two-qubit gate fidelities and times at positions in parameter space where the 2QSS are simultaneously single-qubit sweet spots (1QSS) for the RX and AEON. These results provide a potential route to the realization of high fidelity quantum computation.

Universal quantum computation with electronic qubits in decoherence-free subspace

2008 ◽  
Vol 8 (1&2) ◽  
pp. 96-105
Author(s):  
X.L. Zhang ◽  
M. Feng ◽  
K.L. Gao
Keyword(s):  
Quantum Information ◽  
Quantum Computation ◽  
Degrees Of Freedom ◽  
Quantum Information Processing ◽  
Building Blocks ◽  
Free Electrons ◽  
Single Spin ◽  
Universal Quantum ◽  
Phase Gate ◽  
Decoherence Free Subspace

We investigate how to carry out universal quantum computation deterministically with free electrons in decoherence-free subspace by using polarizing beam splitters, charge detectors, and single-spin rotations. Quantum information in our case is encoded in spin degrees of freedom of the electron-pairs which construct a decoherence-free subspace. We design building blocks for two noncommutable single-logic-qubit gates and a logic controlled phase gate, based on which a universal and scalable quantum information processing robust to dephasing is available in a deterministic way.

Improved Quantum Dot Cellular Automata 4:1 Multiplexer Circuit Unit

2014 ◽  
Vol 2014 (1) ◽  
pp. 37-44 ◽  
Author(s):  
Arighna Sarkar ◽  
◽  
Debarka Mukhopadhyay ◽  
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Quantum Dot Cellular Automata

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

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