NanoProbing on 7 nm FinFET Devices in an SRAM Array: Challenges and Solutions

2019 ◽  
Author(s):  
Anqi Qiu ◽  
William Lowe ◽  
Mridul Arora
Keyword(s):  
Manufacturing Process ◽  
Semiconductor Manufacturing

Abstract Nanoprobing systems have evolved to meet the challenges from recent innovations in the semiconductor manufacturing process. This is demonstrated through an exhibition of standard SRAM measurements on TSMC 7 nm FinFET technology. SEM based nanoprober is shown to meet or exceed the requirements for measuring 7nm technology and beyond. This paper discusses in detail of the best-known methods for nanoprobing on 7nm technology.

An empirical study-based state space model for multilayer overlay errors in the step-scan lithography process

RSC Advances ◽  
2015 ◽  
Vol 5 (126) ◽  
pp. 103901-103906 ◽  
Author(s):  
Fuyun He ◽  
Zhisheng Zhang
Keyword(s):  
Empirical Study ◽  
State Space ◽  
Integrated Circuit ◽  
Manufacturing Process ◽  
Semiconductor Manufacturing ◽  
State Space Model ◽  
Key Factors ◽  
Space Model ◽  
Lithography Process ◽  
Multistage Manufacturing

In semiconductor manufacturing, the multilayer overlay lithography process is a typical multistage manufacturing process; one of the key factors that restrict the reliability and yield of integrated circuit chips is overlay error between the layers.

scholarly journals Investigation of collecting conditions for determination of arsine in working environment of semiconductor manufacturing process.

1991 ◽  
Vol 40 (3) ◽  
pp. 149-152 ◽  
Author(s):  
Michie KOYAMA ◽  
Syokichi CHAKI ◽  
Manabu YAMAMOTO ◽  
Takahiro KUMAMARU
Keyword(s):  
Manufacturing Process ◽  
Semiconductor Manufacturing ◽  
Working Environment

Optimal Parameter Design in Flip Chip Micro-Machining Process for Solder Residue by Using Design of Experiments Approach

2010 ◽  
Vol 126-128 ◽  
pp. 867-872
Author(s):  
Jian Long Kuo ◽  
Chun Cheng Kuo
Keyword(s):  
Design Of Experiments ◽  
Manufacturing Process ◽  
Semiconductor Manufacturing ◽  
Flip Chip ◽  
Optimal Parameter ◽  
Optimal Solution ◽  
Machining Process ◽  
Passive Component ◽  
Quality Properties ◽  
Chip Quality

Since the solder residue is essential in the semiconductor manufacturing process, it has great impact on the flip chip quality considerably. This paper intends to improve the flip chip quality and try to obtain an optimal solution for the system parameters in the flip chip manufacturing process. The SMT manufacturing process is studied for discussion. The amount of solder and the size of solder are selected as the two quality properties. During the flux cleaning process, many solders are left on the passive component side. The balling might flow into the chip. It will cause the bump short in the chip which will affect the quality of the flip chip severely. In this paper, response surface method is adopted as the design of experiments. The objective function and subjective constrained conditions are defined to formulate the optimization problem. The confirmation experimental results are also provided to prove the validity. It is believed that the optimization results are helpful to the improvement of the semiconductor manufacturing process.

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