EVALUATION OF THE HARDWARE COSTS OF IMPLEMENTING A LINEAR CONVOLUTION OPERATOR ON AN FPGA IN BIT-SERIAL ARCHITECTURES

Author(s):  
A. A.  Popov ◽  
1992 ◽  
Vol 139 (3) ◽  
pp. 230 ◽  
Author(s):  
M.A. Hasan ◽  
V.K. Bhargava
Keyword(s):  

Author(s):  
K. Maystrenko ◽  
A. Budilov ◽  
D. Afanasev

Goal. Identify trends and prospects for the development of radar in terms of the use of convolutional neural networks for target detection. Materials and methods. Analysis of relevant printed materials related to the subject areas of radar and convolutional neural networks. Results. The transition to convolutional neural networks in the field of radar is considered. A review of papers on the use of convolutional neural networks in pattern recognition problems, in particular, in the radar problem, is carried out. Hardware costs for the implementation of convolutional neural networks are analyzed. Conclusion. The conclusion is made about the need to create a methodology for selecting a network topology depending on the parameters of the radar task.


2020 ◽  
Vol 26 (2) ◽  
pp. 185-192
Author(s):  
Sunanda Naik ◽  
Pankaj K. Nath

AbstractIn this article, we define a convolution operator and study its boundedness on mixed-norm spaces. In particular, we obtain a well-known result on the boundedness of composition operators given by Avetisyan and Stević in [K. Avetisyan and S. Stević, The generalized Libera transform is bounded on the Besov mixed-norm, BMOA and VMOA spaces on the unit disc, Appl. Math. Comput. 213 2009, 2, 304–311]. Also we consider the adjoint {\mathcal{A}^{b,c}} for {b>0} of two parameter families of Cesáro averaging operators and prove the boundedness on Besov mixed-norm spaces {B_{\alpha+(c-1)}^{p,q}} for {c>1}.


2021 ◽  
Vol 31 (2) ◽  
Author(s):  
Michael Herrmann ◽  
Karsten Matthies

AbstractWe study the eigenvalue problem for a superlinear convolution operator in the special case of bilinear constitutive laws and establish the existence and uniqueness of a one-parameter family of nonlinear eigenfunctions under a topological shape constraint. Our proof uses a nonlinear change of scalar parameters and applies Krein–Rutman arguments to a linear substitute problem. We also present numerical simulations and discuss the asymptotics of two limiting cases.


Author(s):  
Sergio Roldán Lombardía ◽  
Fatih Balli ◽  
Subhadeep Banik

AbstractRecently, cryptographic literature has seen new block cipher designs such as , or that aim to be more lightweight than the current standard, i.e., . Even though family of block ciphers were designed two decades ago, they still remain as the de facto encryption standard, with being the most widely deployed variant. In this work, we revisit the combined one-in-all implementation of the family, namely both encryption and decryption of each as a single ASIC circuit. A preliminary version appeared in Africacrypt 2019 by Balli and Banik, where the authors design a byte-serial circuit with such functionality. We improve on their work by reducing the size of the compact circuit to 2268 GE through 1-bit-serial implementation, which achieves 38% reduction in area. We also report stand-alone bit-serial versions of the circuit, targeting only a subset of modes and versions, e.g., and . Our results imply that, in terms of area, and can easily compete with the larger members of recently designed family, e.g., , . Thus, our implementations can be used interchangeably inside authenticated encryption candidates such as , or in place of .


Author(s):  
Maxime Martineau ◽  
Romain Raveaux ◽  
Donatello Conte ◽  
Gilles Venturini

Sign in / Sign up

Export Citation Format

Share Document