scholarly journals Architecture and implementation of a high frame-rate stereo vision system

2021 ◽  
Author(s):  
Jamin Islam
Keyword(s):  
Integrated Circuits ◽  
Stereo Vision ◽  
High Speed ◽  
Vision System ◽  
Low Cost ◽  
Cost Effective ◽  
Frame Rate ◽  
Superior Performance ◽  
High Frame Rate ◽  
Stereo Vision System

For the purpose of autonomous satellite grasping, a high-speed, low-cost stereo vision system is required with high accuracy. This type of system must be able to detect an object and estimate its range. Hardware solutions are often chosen over software solutions, which tend to be too slow for high frame-rate applications. Designs utilizing field programmable gate arrays (FPGAs) provide flexibility and are cost effective versus solutions that provide similar performance (i.e., Application Specific Integrated Circuits). This thesis presents the architecture and implementation of a high frame-rate stereo vision system based on an FPGA platform. The system acquires stereo images, performs stereo rectification and generates disparity estimates at frame-rates close to 100 fpSi and on a large-enough FPGA, it can process 200 fps. The implementation presents novelties in performance and in the choice of the algorithm implemented. It achieves superior performance to existing systems that estimate scene depth. Furthermore, it demonstrates equivalent accuracy to software implementations of the dynamic programming maximum likelihood stereo correspondence algorithm.

scholarly journals Architecture and implementation of a high frame-rate stereo vision system

2021 ◽  
Author(s):  
Jamin Islam
Keyword(s):  
Integrated Circuits ◽  
Stereo Vision ◽  
High Speed ◽  
Vision System ◽  
Low Cost ◽  
Cost Effective ◽  
Frame Rate ◽  
Superior Performance ◽  
High Frame Rate ◽  
Stereo Vision System

For the purpose of autonomous satellite grasping, a high-speed, low-cost stereo vision system is required with high accuracy. This type of system must be able to detect an object and estimate its range. Hardware solutions are often chosen over software solutions, which tend to be too slow for high frame-rate applications. Designs utilizing field programmable gate arrays (FPGAs) provide flexibility and are cost effective versus solutions that provide similar performance (i.e., Application Specific Integrated Circuits). This thesis presents the architecture and implementation of a high frame-rate stereo vision system based on an FPGA platform. The system acquires stereo images, performs stereo rectification and generates disparity estimates at frame-rates close to 100 fpSi and on a large-enough FPGA, it can process 200 fps. The implementation presents novelties in performance and in the choice of the algorithm implemented. It achieves superior performance to existing systems that estimate scene depth. Furthermore, it demonstrates equivalent accuracy to software implementations of the dynamic programming maximum likelihood stereo correspondence algorithm.

Development of a Low-Cost, High-Speed Stereo Vision System Using a CMOS Imager and DSP

2011 ◽  
Vol 5 (3) ◽  
pp. 445-451
Author(s):  
Makoto Yamashita ◽  
◽  
Noriaki Maru ◽  
Keyword(s):  
Stereo Vision ◽  
High Speed ◽  
Vision System ◽  
Low Cost ◽  
Small Scale ◽  
Target Point ◽  
Real Time Processing ◽  
Cmos Imager ◽  
Stereo Vision System ◽  
Target Track

This article presents the development of a low-cost, high-speed stereo vision system for embedded use employing a mass-produced CMOS imager and a commercially available DSP. We use the system to acquire an image of 96×96 pixels in a period of 1 ms. We embed a read region movement control and a target track function into the system and successfully track a target point within a period of 3 ms. The difference between this high-speed stereo vision system and traditional ones lies in that this system is intended to be used even in a small-scale control system using a microcomputer. We limit the capacity of the image memory in which acquired pixel data is temporarily stored and performed real time processing. As a result, we eliminate frame memory and thus simplify its corresponding circuit. This allows the system to be reduced in size, power consumption, and cost, thereby making the system appropriate for embedded devices, batterypowered robots, and the like.

Low-cost FPGA stereo vision system for real time disparity maps calculation

2012 ◽  
Vol 36 (4) ◽  
pp. 281-288 ◽  
Author(s):  
Paolo Zicari ◽  
Stefania Perri ◽  
Pasquale Corsonello ◽  
Giuseppe Cocorullo
Keyword(s):  
Real Time ◽  
Stereo Vision ◽  
Vision System ◽  
Low Cost ◽  
Stereo Vision System ◽  
Disparity Maps

An Intelligent High-Frame-Rate Video Logging System for Abnormal Behavior Analysis

2011 ◽  
Vol 23 (1) ◽  
pp. 53-65 ◽  
Author(s):  
Yao-DongWang ◽  
◽  
Idaku Ishii ◽  
Takeshi Takaki ◽  
Kenji Tajima ◽  
...  
Keyword(s):  
Real Time ◽  
Video Processing ◽  
High Speed ◽  
Vision System ◽  
Video Recording ◽  
Frame Rate ◽  
Abnormal Behavior ◽  
High Frame Rate ◽  
Abnormal Behavior Detection ◽  
Abnormal Behaviors

This paper introduces a high-speed vision system called IDP Express, which can execute real-time image processing and High-Frame-Rate (HFR) video recording simultaneously. In IDP Express, 512×512 pixel images from two camera heads and the processed results on a dedicated FPGA (Field Programmable Gate Array) board are transferred to standard PC memory at a rate of 1000 fps or more. Owing to the simultaneous HFR video processing and recording, IDP Express can be used as an intelligent video logging system for long-term high-speed phenomenon analysis. In this paper, a real-time abnormal behavior detection algorithm was implemented on IDP-Express to capture HFR videos of crucial moments of unpredictable abnormal behaviors in high-speed periodic motions. Several experiments were performed for a high-speed slider machine with repetitive operation at a frequency of 15 Hz and videos of the abnormal behaviors were automatically recorded to verify the effectiveness of our intelligent HFR video logging system.

scholarly journals Development of a Low Cost and Path-free Autonomous Patrol System Based on Stereo Vision System and Checking Flags

2020 ◽  
Vol 10 (3) ◽  
pp. 974
Author(s):  
Chien-Wu Lan ◽  
Chi-Yao Chang
Keyword(s):  
Stereo Vision ◽  
Radio Frequency Identification ◽  
Vision System ◽  
Low Cost ◽  
Color Pattern ◽  
Depth Information ◽  
Rfid Tag ◽  
Intruder Detection ◽  
Stereo Vision System ◽  
Identification Function

Nowadays, security guard patrol services are becoming roboticized. However, high construction prices and complex systems make patrol robots difficult to be popularized. In this research, a simplified autonomous patrolling robot is proposed, which is fabricated by upgrading a wheeling household robot with stereo vision system (SVS), radio frequency identification (RFID) module, and laptop. The robot has four functions: independent patrolling without path planning, checking, intruder detection, and wireless backup. At first, depth information of the environment is analyzed through SVS to find a passable path for independent patrolling. Moreover, the checkpoints made with RFID tag and color pattern are placed in appropriate positions within a guard area. While a color pattern is detected by the SVS, the patrolling robot is guided to approach the pattern and check its RFID tag. For more, the human identification function of SVS is used to detect an intruder. While a skeleton information of the human is analyzed by SVS, the intruder detection function is triggered, then the robot follows the intruder and record the images of the intruder. The recorded images are transmitted to a server through Wi-Fi to realize the remote backup, and users can query the recorded images from the network. Finally, an experiment is made to test the functions of the autonomous patrolling robot successfully.

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