scholarly journals All-digital ΔΣ time-to-digital converter with bi-directional gated delay line time integrator

2021 ◽  
Author(s):  
Parth Parekh
Keyword(s):  
Delay Line ◽  
Building Blocks ◽  
Cmos Technology ◽  
Time Variable ◽  
Noise Shaping ◽  
Digital Converter ◽  
First Order ◽  
Time To Digital Converter ◽  
Oversampling Ratio ◽  
Signal Band

This report presents a low-power time integrator and its applications in an all-digital first-order ΔΣ time-to-digital converter (TDC). Time-to-Digital Converter (TDC) that map a time variable to a digital code is the most important building blocks of time-mode circuits. The time integrator is realized using a bi-directional gated delay line (BD-GDL) with time variable to be integrated as the gating signal. The integration of the time variable is obtained via the accumulation of the charge of the load capacitor and the logic state of gated delay stages. Issues affecting the performance of the time integrator and TDC are examined. The all-digital first-order ΔΣ TDC utilizing the time integrator was designed in using IBM 130 nm 1.2 V CMOS technology and analysed using Spectre ASP from Cadence Design Systems with BSIM4 models. A sinusoid time input of 333 ps amplitude and 231 kHz frequency with an oversampling ratio 68 was digitized by the modulator. The TDC provides first-order noise-shaping and a SNR of 34.64 dB over the signal band 48.27 ~ 231 kHz while consuming 293.8 μW.

scholarly journals All-digital ΔΣ time-to-digital converter with bi-directional gated delay line time integrator

2021 ◽  
Author(s):  
Parth Parekh
Keyword(s):  
Delay Line ◽  
Building Blocks ◽  
Cmos Technology ◽  
Time Variable ◽  
Noise Shaping ◽  
Digital Converter ◽  
First Order ◽  
Time To Digital Converter ◽  
Oversampling Ratio ◽  
Signal Band

This report presents a low-power time integrator and its applications in an all-digital first-order ΔΣ time-to-digital converter (TDC). Time-to-Digital Converter (TDC) that map a time variable to a digital code is the most important building blocks of time-mode circuits. The time integrator is realized using a bi-directional gated delay line (BD-GDL) with time variable to be integrated as the gating signal. The integration of the time variable is obtained via the accumulation of the charge of the load capacitor and the logic state of gated delay stages. Issues affecting the performance of the time integrator and TDC are examined. The all-digital first-order ΔΣ TDC utilizing the time integrator was designed in using IBM 130 nm 1.2 V CMOS technology and analysed using Spectre ASP from Cadence Design Systems with BSIM4 models. A sinusoid time input of 333 ps amplitude and 231 kHz frequency with an oversampling ratio 68 was digitized by the modulator. The TDC provides first-order noise-shaping and a SNR of 34.64 dB over the signal band 48.27 ~ 231 kHz while consuming 293.8 μW.

A 9 Bit, 3.6 ps Resolution Pipeline Time-to-Digital Converter

2019 ◽  
Vol 29 (08) ◽  
pp. 2050124
Author(s):  
Farshad Goodarzi ◽  
Siroos Toofan
Keyword(s):  
Fine Structure ◽  
Delay Line ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Digital Converter ◽  
Time Intervals ◽  
Wide Linear Range ◽  
Time To Digital Converter ◽  
Good Linearity ◽  
Time Amplifier

This paper describes a 9-bit time-to-digital converter (TDC) with 3.6 ps resolution. The resolution of 3.6 ps is achieved using coarse and fine structure. The structure of the proposed two-step pipeline TDC is composed of a 4-bit coarse TDC (CTDC) based on delay line and a 5-bit fine TDC (FTDC) based on an SAR-CD algorithm where a Time Amplifier (TA) is used between them. Since TA amplifies the time intervals in different stages of delay line to achieve accurate gain with wide linear range. Therefore, the TDC has good linearity. The proposed TDC has Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) errors of 1.6 and 2.6 LSB, respectively. This TDC was designed in 0.18[Formula: see text][Formula: see text]m CMOS technology. Using a supply voltage of 1.8[Formula: see text]V, the proposed TDC consumes 1.88[Formula: see text]mW at 25 MS/s throughput.

scholarly journals Increasing a Resolution of Time to Digital Converter

2017 ◽  
Vol 9 (3) ◽  
pp. 318-323
Author(s):  
Marijan Jurgo ◽  
Romualdas Navickas
Keyword(s):  
Delay Time ◽  
Noise Level ◽  
Delay Line ◽  
Cmos Technology ◽  
Phase Detector ◽  
Quantization Noise ◽  
Time Interval ◽  
Digital Converter ◽  
Technological Parameters ◽  
Time To Digital Converter

Time to digital converter (TDC) is one of the main blocks of all-digital frequency synthesizer (FS), where it is used as phase detector. The output of TDC is digital, therefore it introduces quantization noise to the output of FS. The resolution of TDC has to be increased, to improve phase noise level at the output of FS. It can be achieved by improving CMOS technology or structure of the TDC. The simplest TDC is based on inverter delay line. Its resolution is inversely proportional to the time interval, which can be measured with such TDC, i.e. delay time of the inverter. Decreasing of this delay is essence of technological increasing of TDC’s resolution. In this work the dependency of inverter delay on technological parameters is shown and its value is calculated in 65 nm CMOS technology. Calculations show, that in this technology delay time of the inverter can vary from 7 ps to 54 ps. If the design is restricted to the usage of specific CMOS technology, in which inverter’s delay does not ensure needed noise level at the output of FS, structure of the TDC needs to be improved. The aim of this improvement is to measure time interval smaller than inverter’s delay. Some of the TDC structures, which can measure sub-inverter delay time, are reviewed in this work: TDC – Vernier delay line, TDC – 2D Vernier plane, stochastic, ring and multistage TDCs.

Sign in / Sign up

Export Citation Format

Share Document