Serial RRAM Cell for Secure Bit Concealing

Non-volatile memory cells are exposed to adversary attacks since any active countermeasure is useless when the device is powered off. In this context, this work proposes the association of two serial RRAM devices as a basic cell to store sensitive data, which could solve this bothersome problem. This cell has three states: ‘1’, ‘0’, and masked. When the system is powered off or the data is not used, the cell is set to the masked state, where the cell still stores a ‘1’ or a ‘0’ but a malicious adversary is not capable of extracting the stored value using reverse engineering techniques. Before reading, the cell needs to be unmasked and it is masked afterwards until the next reading request. The operation of the cell also provides robustness against side-channel attacks. The presented experimental results confirm the validity of the proposal.

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Side channel attacks and the non volatile memory of the future

Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems - CASES '12 ◽

10.1145/2380403.2380413 ◽

2012 ◽

Cited By ~ 1

Author(s):

Zoya Dyka ◽

Christian Walczyk ◽

Damian Walczyk ◽

Christian Wenger ◽

Peter Langendoerfer

Keyword(s):

Side Channel ◽

Side Channel Attacks ◽

The Future ◽

Non Volatile Memory ◽

Volatile Memory

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Code Polymorphism Meets Code Encryption: Confidentiality and Side-Channel Protection of Software Components

Digital Threats: Research and Practice ◽

10.1145/3487058 ◽

2021 ◽

Author(s):

Lionel Morel ◽

Damien Courousse ◽

Thomas Hiscock

Keyword(s):

Reverse Engineering ◽

Cyber Attacks ◽

Side Channel ◽

Security Level ◽

Software Components ◽

Side Channel Attacks ◽

Sensitive Data ◽

Prototype Implementation ◽

Counter Measures ◽

Observable Behaviour

Cyber-attacks combine several techniques to compromise device's functionality, recover sensitive data or unveil IP design. Combined counter-measures are needed to address these complex attacks as a whole. We address attacks that rely on reverse engineering to recover application code and side-channel attacks to access sensitive data. We present POLEN, a toolchain and a processor architecture that combines two countermeasures: code encryption and code polymorphism to thwart such complex attacks. Code encryption reduces the useful information in memory dumps, preventing reverse engineering, by encrypting machine instructions before its deployment, and instructions are only decrypted inside the CPU. Code polymorphism regularly changes the observable behaviour of the program, making it unpredictable for an attacker, and reducing the possibility to exploit side-channel leakages. Using many configuration parameters, POLEN gives the developer the ability to adapt the security level to its application. We present our prototype implementation, based on the RISC-V Spike simulator and a modified LLVM toolchain. We demonstrate that POLEN reduces side-channel leakages through leakage assessments metrics. We show that POLEN achieves a good level of security against side-channel attacks while maintaining acceptable overheads on program performance.

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