Linearity Enhancement of VCO-Based Continuous-Time Delta-Sigma ADCs Using Digital Feedback Residue Quantization

A linearity enhancement scheme for voltage-controlled oscillator (VCO)-based continuous-time (CT) delta-sigma (ΔΣ) analog-to-digital converters (ADCs) is proposed. Unlike conventional input feedforwarding techniques, the proposed feedforwarding scheme using digital feedback residue quantization (DFRQ) can avoid the analog summing amplifier, allow intrinsic anti-aliasing filtering (AAF) characteristic, and cause no switching noise injection into the input. A VCO-based CT ΔΣ ADC adapting the proposed DFRQ enables residue-only processing in the quantizer, avoiding the degradation of signal-to-noise and distortion ratio (SNDR) due to VCO nonlinearity. The use of DFRQ also reduces the voltage swing of integrators without the drawbacks caused by conventional input feedforwarding techniques. The performance evaluation results indicate that the proposed VCO-based CT ΔΣ ADC with DFRQ provides 30.3-dB SNDR improvement, reaching up to 83.5-dB in 2-MHz signal bandwidth.

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VCO-BASED CONTINUOUS-TIME SIGMA DELTA ADC BASED ON A DUAL-VCO-QUANTIZER-LOOP STRUCTURE

Journal of Circuits System and Computers ◽

10.1142/s0218126613400136 ◽

2013 ◽

Vol 22 (09) ◽

pp. 1340013 ◽

Cited By ~ 1

Author(s):

Z. T. XU ◽

X. L. ZHANG ◽

J. Z. CHEN ◽

S. G. HU ◽

Q. YU ◽

...

Keyword(s):

Continuous Time ◽

Signal To Noise Ratio ◽

Quantization Noise ◽

Cmos Process ◽

Voltage Controlled Oscillator ◽

Loop Structure ◽

Signal To Noise ◽

Sigma Delta ◽

Analog To Digital ◽

Sigma Delta Adc

This paper explores a continuous time (CT) sigma delta (ΣΔ) analog-to-digital converter (ADC) based on a dual-voltage-controlled oscillator (VCO)-quantizer-loop structure. A third-order filter is adopted to reduce quantization noise and VCO nonlinearity. Even-order harmonics of VCO are significantly reduced by the proposed dual-VCO-quantizer-loop structure. The prototype with 10 MHz bandwidth and 400 MHz clock rate is designed using a 0.18 μm RF CMOS process. Simulation results show that the signal-to-noise ratio and signal-to-noise distortion ratio (SNDR) are 76.9 and 76 dB, respectively, consuming 37 mA at 1.8 V. The key module of the ADC, which is a 4-bit VCO-based quantizer, can convert the voltage signal into a frequency signal and quantize the corresponding frequency to thermometer codes at 400 MS/s.

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A High-Resolution and Low Offset Delta-Sigma Analog to Digital Converter for Detecting Photoplethysmography Signal

ASME 2021 30th Conference on Information Storage and Processing Systems ◽

10.1115/isps2021-65248 ◽

2021 ◽

Author(s):

Eka Fitrah Pribadi ◽

Rajeev Kumar Pandey ◽

Paul C.-P. Chao

Keyword(s):

High Resolution ◽

Continuous Time ◽

Operational Amplifier ◽

High Frequency ◽

Analog To Digital Converter ◽

Digital Converter ◽

Analog To Digital ◽

Delta Sigma Modulator ◽

Delta Sigma ◽

Low Offset

Abstract A high-resolution, low offset delta-sigma analog to digital converter for detecting photoplethysmography (PPG) signal is presented in this study. The PPG signal is a bio-optical signal incorporated with heart functionality and located in the range of 0.1–10 Hz. The location to get PPG signal is on a pulsating artery. Thus the delta-sigma analog-to-digital (DS ADC) converter is designed specifically in that range. However, the DS ADC circuitry suffers from 1/f noise under 10 Hz frequency range. A chopper based operational amplifier is implemented in DS ADC to push the 1/f noise into high-frequency noise. The dc offset of the operational amplifier is also pushed to the high-frequency region. The DS ADC circuitry consists of a second-order continuous-time delta-sigma modulator. The delta-sigma modulator circuitry is designed and simulated using TSMC 180 nm technology. The continuous-time delta-sigma modulator active area layout is 746μm × 399 μm and fabricated using TSMC 180 nm technology. It operates in 100 Hz bandwidth and 4096 over-sampling ratios. The SFDR of the circuit is above 70 dB. The power consumption of the delta-sigma modulator is 35.61μW. The simulation is performed in three different kinds of corner, SS, TT, and FF corner, to guarantee the circuitry works in different conditions.

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