Linearity Enhancement of VCO-Based Continuous-Time Delta-Sigma ADCs Using Digital Feedback Residue Quantization

A linearity enhancement scheme for voltage-controlled oscillator (VCO)-based continuous-time (CT) delta-sigma (ΔΣ) analog-to-digital converters (ADCs) is proposed. Unlike conventional input feedforwarding techniques, the proposed feedforwarding scheme using digital feedback residue quantization (DFRQ) can avoid the analog summing amplifier, allow intrinsic anti-aliasing filtering (AAF) characteristic, and cause no switching noise injection into the input. A VCO-based CT ΔΣ ADC adapting the proposed DFRQ enables residue-only processing in the quantizer, avoiding the degradation of signal-to-noise and distortion ratio (SNDR) due to VCO nonlinearity. The use of DFRQ also reduces the voltage swing of integrators without the drawbacks caused by conventional input feedforwarding techniques. The performance evaluation results indicate that the proposed VCO-based CT ΔΣ ADC with DFRQ provides 30.3-dB SNDR improvement, reaching up to 83.5-dB in 2-MHz signal bandwidth.

Simulation and Analysis of different CMOS Full Adders for Delay Optimisation

Full adder circuit is one among the fundamental and necessary digital part. The full adder is be a part of microprocessors, digital signal processors etc. It's needed for the arithmetic and logical operations. Full adder design enhancements are necessary for recent advancement. The requirement of an adder cell is to provide high speed, consume low power and provide high voltage swing. This paper analyses and compares 3 adders with completely different logic designs (Conventional, transmission gate & pseudo NMOS) for transistor count, power dissipation and delay. The simulation is performed in Cadence virtuoso tool with accessible GPDK – 180nm kit. Transmission gate full adder has sheer advantage of high speed, fewer space and also it shows higher performance in terms of delay. Keywords: Delay, power dissipation, voltage, transistor sizing.

Starter for Voltage Boost Converter to Harvest Thermoelectric Energy for Body-Worn Sensors

This paper examines the suitability of selected configurations of ultra-low voltage (ULV) oscillators as starters for a voltage boost converter to harvest energy from a thermoelectric generator (TEG). Important properties of particularly promising configurations, suitable for on-chip implementation are compared. On this basis, an improved oscillator with a low startup voltage and a high output voltage swing is proposed. The applicability of n-channel native MOS transistors with negative or near-zero threshold voltage in ULV oscillators is analyzed. The results demonstrate that a near-zero threshold voltage transistor operating in the weak inversion region is most advantageous for the considered application. The obtained results were used as a reference for design of a boost converter starter intended for integration in 180-nm CMOS X-FAB technology. In the selected technology, the most suitable transistor available with a negative threshold voltage was used. Despite using a transistor with a negative threshold voltage, a low startup voltage of 29 mV, a power consumption of 70 µW, and power conversion efficiency of about 1.5% were achieved. A great advantage of the proposed starter is that it eliminates a multistage charge pump necessary to obtain a voltage of sufficient value to supply the boost converter control circuit.

A 10 Gbps 4-PAM CMOS serial link transmitter with pre-emphasis

This thesis presents the design of 10 Gbps 4-PAM CMOS serial link transmitters. A new area-power efficient fully differential CMOS current-mode serial link transmitter with a proposed 2/4-PAM signaling configuration and a new pre-emphasis scheme is presented. The pre-emphasis inthe analog domain and the use of de-emphasis approach decres pre-emphasis power and chip area. The high-speed operation of the transmitter is achieved from the small voltage swing of critical nodes of the transmitter, shunt peaking with active inductors, multiplexing-at-input approach, the distributed multiplexing nodes, and the low characteristic impedance of the channels. The fully differential and bidirectional current-mode signaling minimizes the noise injected to the power and ground rails and the electromagnetic interference exerted from the channels to neighboring devices. A PLL containing a proposed five-stage VCO is implemented to generate multi-phase on -chip clocks. The proposed VCO minimized the phase noise by keeping a constant rising and falling time. Simulation results demonstrate that the current received at the far end of a 10 cm FR-4 microstriop has a 4-PAM current eye width of 185 ps and eye hight of 1.21 mA. It consumes 57.6 mW power with differnetial delay block, or 19.2 mW power with inverter buffer chain. The total transistor area of the transmitter is 26.845 ....excluding the delay block.

A 10 Gbps 4-PAM CMOS serial link transmitter with pre-emphasis

This thesis presents the design of 10 Gbps 4-PAM CMOS serial link transmitters. A new area-power efficient fully differential CMOS current-mode serial link transmitter with a proposed 2/4-PAM signaling configuration and a new pre-emphasis scheme is presented. The pre-emphasis inthe analog domain and the use of de-emphasis approach decres pre-emphasis power and chip area. The high-speed operation of the transmitter is achieved from the small voltage swing of critical nodes of the transmitter, shunt peaking with active inductors, multiplexing-at-input approach, the distributed multiplexing nodes, and the low characteristic impedance of the channels. The fully differential and bidirectional current-mode signaling minimizes the noise injected to the power and ground rails and the electromagnetic interference exerted from the channels to neighboring devices. A PLL containing a proposed five-stage VCO is implemented to generate multi-phase on -chip clocks. The proposed VCO minimized the phase noise by keeping a constant rising and falling time. Simulation results demonstrate that the current received at the far end of a 10 cm FR-4 microstriop has a 4-PAM current eye width of 185 ps and eye hight of 1.21 mA. It consumes 57.6 mW power with differnetial delay block, or 19.2 mW power with inverter buffer chain. The total transistor area of the transmitter is 26.845 ....excluding the delay block.

Analysis and Design of a Fully-Integrated High-Power Differential CMOS T/R Switch and Power Amplifier Using Multi-Section Impedance Transformation Technique

In this paper, a new topology for a high-power single-pole-double-throw (SPDT) antenna switch is presented, and its loss mechanisms are fully analyzed. The differential architecture is employed in the proposed switch implementation to prevent unwanted channel formations of OFF-state Rx switch transistors by relieving the voltage swing over the Rx switch devices. In addition to that, the load impedance seen by the Tx switch is stepped down to reduce the voltage swing even more, allowing the antenna switch to handle a high-power signal without distortions. To drop the switch operating impedance, two matching networks are required at the input and the output of the Tx switch, respectively, and they are carefully implemented considering the integration issue of the front-end circuitries. From the loss analysis of the whole signal path, an optimum switch operating impedance is decided in view of a trade-off between power handling capability and insertion loss of the antenna switch. The insertion loss of the proposed design is compared to the conventional design with electromagnetic (EM) simulated transformer and inductors. The proposed antenna switch is implemented in a standard 0.18 µm CMOS process, and all switch devices adopt the deep n-well structure. The measured performance of the proposed transmitter front-end chain shows a 1 dB compression point (P1dB) of 32.1 dBm with 38.3% power-added efficiency (PAE) at 1.9 GHz.

Energy Efficient Full Swing GDI based Adder Architecture for Arithmetic Applications

Adders are one of the most important digital components used in any arithmetic applications. Many improvements in past have been made to improve its architecture. In this paper, we present two new symmetric designs for Energy efficient full adder cells featuring GDI (Gate-Diffusion Input) logic. The main design objectives for these adder modules are to operate at Low-Power with reduced area but also provide full-voltage swing. In the first (AEG-FA) design, a new approach of Inverted and Non-Inverted Carry-ins were taken to give complementary Carry-out and Sum with desired performance. These were then applied in different combinations to form higher bit width Adder architecture. This provides a higher degree of design freedom to target a wide range of applications, hence reducing design efforts. The second (PEG-FA) design is based on conventional approach which tries to reduce the critical path delay and lower switching activity in GDI circuit, providing Low-Power and high speed digital component at full voltage swing circuit. Many of the previously reported adders in literature suffered from the problems of low-swing and high noise when operated at low supply voltages. These two new designs successfully operate at low voltage with high signal integrity and driving capability. In order to evaluate the performance of proposed full adders, we incorporated 8-bit ripple carry adders. The studied circuits are optimized for energy efficiency using 45 nm CMOS process technology. The comparison between these novel circuits with standard full adder cells shows improvement in terms of Area, Delay, Power and Power-Delay-Product (PDP), Area-Delay Product (ADP), Area-Power Product (APP). At architecture level proposed adder shows 12.8% over CMOS, 14.8% over hybrid and 11.4% over other GDI logic power savings, by having almost 55% reduction in area.

The Design of 50 GHz Gallium Arsenide Electro-Optic Modulator Arrays for Satellite Communications Systems

Considerations are presented for the design of GaAs traveling-wave electro-optic modulator arrays for space data-link applications. Central to the modulator design is a low loss folded optical configuration giving direct, straight-line radio frequency (RF) access at one end of the device, with all fiber-optical ports at the opposite end. This configuration is a critical enabler for the close-packed monolithic modulator arrays needed for multi-channel applications. It also leads to much more compact packaging, improved fiber handling and contributes to high modulation bandwidths with low ripple by eliminating directional change in the RF feed arrangements. Both single Mach-Zehnder (MZ) and monolithic dual-parallel (IQ) modulators have been assessed up to 70 GHz, with bandwidths around 50 GHz achieved with a low-frequency ON/OFF voltage swing (Vπ) of 4.6 V (a voltage. length product of 8.3 Vcm). The folded devices can be significantly more compact than conventional ‘straight in-line’ modulators, while a modest array of devices (e.g., ×4) can be accommodated in a package of similar dimensions to a single modulator. Design considerations for monolithic arrays of independently addressed MZ modulators (each with its own input fiber) are discussed and practical configurations proposed.

Design and Analysis of AlGaN/InGaN/GaN and InAlN/InGaN/GaN HEMTs for High-Power Wide Bandwidth Applications

We present the stable transconductance operation of InGaN/GaN composite channel based HEMTs. LG = 55 nm AlGaN/InGaN/GaN (Device A) and InAlN/InGaN/GaN (Device B) HEMTs were proposed and investigated its operational characteristics using numerical simulation. Existence of deeper potential well, the proposed HEMTs possesses high 2DEG (two-dimensional electron gas) density, enhanced electron confinement, and improved electron mobility. As a result, the device shows enhanced current density, and high linearity operation. Furthermore, Al0.04Ga0.96N superlative back-barrier significantly reduces the buffer leakage current resulting in improved breakdown voltage (VBR). The proposed device A (device B) exhibited 2.81 (5) A/mm of output current density, 0.669 (0.7273) S/mm, 4 (7) V of GVS (gate voltage swing), 55.3 (43.5) V of breakdown voltage, and 252/263 (275/289) GHz of FT/FMAX. This excellent device performances illustrates the potential of InGaN/GaN channel HEMTs for future wide-band telecommunication, radio astronomy, radar and space applications.