scholarly journals Special Issue on Networks-on-Chip Again on the Rise: From Emerging Applications to Emerging Technologies

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1570
Author(s):  
Davide Bertozzi ◽  
José L. Abellán ◽  
Mahdi Nikdast
Keyword(s):  
Interconnection Networks ◽  
Emerging Technologies ◽  
Special Issue ◽  
Networks On Chip ◽  
On Chip

Twenty years after the advent of interconnection networks to tackle the on-chip communication bottleneck [...]

A Design Methodology of MIN-Based Network for MPPSoC on Reconfigurable Architecture

2011 ◽  
pp. 209-234
Author(s):  
Y. Aydi ◽  
M. Baklouti ◽  
Ph. Marquet ◽  
M. Abid ◽  
J.L. Dekeyser
Keyword(s):  
Communication Networks ◽  
Interconnection Networks ◽  
Design Methodology ◽  
Parallel Systems ◽  
Parallel Applications ◽  
Multistage Interconnection Networks ◽  
Networks On Chip ◽  
Data Intensive ◽  
Cost Metrics ◽  
On Chip

Massive parallel processing systems, particularly Single Instruction Multiple Data architectures, play a crucial role in the field of data intensive parallel applications. One of the primary goals in using these systems is their scalability and their linear increase in processing power by increasing the number of processing units. However, communication networks are the big challenging issue facing researchers. One of the most important networks on chip for parallel systems is the multistage interconnection network. In this paper, we propose a design methodology of multistage interconnection networks for massively parallel systems on chip. The framework covers the design step from algorithm level to RTL. We first develop a functional formalization of MIN-based on-chip network at a high level of abstraction. The specification and the validation of the model have been defined in the logic of ACL2 proving system. The main objective in this step is to provide a formal description of the network that integrates architectural parameters which have a huge impact on design costs. After validating the functional model, step 2 consists in the design and the implementation of the Delta multistage networks on chip dedicated to parallel multi-cores architectures on reconfigurable platforms FPGA. In the last step, we propose an evaluation methodology based on performance and cost metrics to evaluate different topologies of dynamic network through data parallel applications with different number of cores. We also show in the proposed framework that multistage interconnection networks are cost-effective high performance networks for parallel SOCs.

Special issue on networks on chip

2004 ◽  
Vol 50 (2-3) ◽  
pp. 61-63 ◽  
Author(s):  
Axel Jantsch ◽  
Johnny Öberg ◽  
Hannu Tenhunen
Keyword(s):  
Special Issue ◽  
Networks On Chip ◽  
On Chip

Special Issue on Networks-on-Chip and Memories for Multicore Architectures

2014 ◽  
Vol 38 (4) ◽  
pp. 253
Author(s):  
Diana Goehringer ◽  
Hamid Sarbazi-Azad ◽  
Rainer Stotzka
Keyword(s):  
Multicore Architectures ◽  
Special Issue ◽  
Networks On Chip ◽  
On Chip

scholarly journals Delta Multi-Stage Interconnection Networks for Scalable Wireless On-Chip Communication

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 913 ◽  
Author(s):  
Sirine Mnejja ◽  
Yassine Aydi ◽  
Mohamed Abid ◽  
Salvatore Monteleone ◽  
Vincenzo Catania ◽  
...  
Keyword(s):  
Interconnection Networks ◽  
Interconnection Network ◽  
Average Delay ◽  
Networks On Chip ◽  
Energy Profiles ◽  
Multi Stage ◽  
Systems On Chip ◽  
Viable Solution ◽  
On Chip ◽  
Scalable Communication

The Network-on-Chip (NoC) paradigm emerged as a viable solution to provide an efficient and scalable communication backbone for next-generation Multiprocessor Systems-on-Chip. As the number of integrated cores keeps growing, alternatives to the traditional multi-hop wired NoCs, such as wireless Networks-on-Chip (WiNoCs), have been proposed to provide long-range communications in a single hop. In this work, we propose and analyze the integration of the Delta Multistage Interconnection Network (MINs) as a backbone for wireless-enabled NoCs. After extending the well-known Noxim platform to implement a cycle-accurate model of a wireless Delta MIN, we perform a comprehensive set of SystemC simulations to analyze how wireless-augmented Delta MINs can potentially lead to an improvement in both average delay and saturation. Further, we compare the results obtained with traditional mesh-based topologies, reporting energy profiles that show an overall energy cost reduced on both wired/wireless scenarios.

A Kind of Hierarchical Ring Interconnection Networks-on-Chip

2010 ◽  
Vol 33 (2) ◽  
pp. 326-334 ◽  
Author(s):  
Wei WANG ◽  
Lin QIAO ◽  
Guang-Wen YANG ◽  
Zhi-Zhong TANG
Keyword(s):  
Interconnection Networks ◽  
Networks On Chip ◽  
On Chip

scholarly journals Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures

2010 ◽  
Vol 2010 ◽  
pp. 1-15 ◽  
Author(s):  
Ludovic Devaux ◽  
Sana Ben Sassi ◽  
Sebastien Pillement ◽  
Daniel Chillet ◽  
Didier Demigny
Keyword(s):  
Interconnection Networks ◽  
Interconnection Network ◽  
Dynamic Reconfiguration ◽  
Computation Time ◽  
Reconfigurable Architectures ◽  
Partial Reconfiguration ◽  
Dynamic Management ◽  
Networks On Chip ◽  
Communication Architectures ◽  
On Chip

The dynamic and partial reconfiguration of FPGAs enables the dynamic placement in reconfigurable zones of the tasks that describe an application. However, the dynamic management of the tasks impacts the communications since tasks are not present in the FPGA during all computation time. So, the task manager should ensure the allocation of each new task and their interconnection which is performed by a flexible interconnection network. In this article, various communication architectures, in particular interconnection networks, are studied. Each architecture is evaluated with respect to its suitability for the paradigm of the dynamic and partial reconfiguration in FPGA implementations. This study leads us to propose the DRAFT network that supports the communication constraints into the context of dynamic reconfiguration. We also present DRAGOON, the automatic generator of networks, which allows to implement and to simulate the DRAFT topology. Finally, DRAFT and the two most popular Networks-on-Chip are implemented in several configurations using DRAGOON, and compared considering real implementation results.

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