The classical planar Metal Oxide Semiconductor
Field Effect Transistors (MOSFET) is fabricated by oxidation of
a semiconductor namely Silicon. In this generation, an advanced
technique called 3D system architecture FETs, are introduced for
high performance and low power quality of devices. Based on the
limitations of Short Channel Effect (SCE), Silicon (Si) FET
cannot be scaled under 10nm. Hence various performing
measures like methods, principles, and geometrics are done to
upscale the semiconductor. CMOS using alternate channel
materials like GE and III-Vs on substrates is a highly anticipated
technique for developing nanowire structures. By considering
these issues, in this paper, we developed a simulation model that
provides accurate results basing on Gate layout and multi-gate
NW FET's so that the scaling can be increased few nanometers
long and performance limits gradually increases. The model
developed is SILVACO that tests the action of FET with different
gate oxide materials.
Distributed storage for intermittent energy sources: Control design and performance limits
