scholarly journals Enhancing Apple Maturation Recognition Performance Based on Field Programmable Gate Array Implementation

Author(s):  
Fouad H. Awad ◽  
Mohammed A. Fadhel ◽  
Khattab M. Ali Alheeti ◽  
Omran Al-Shamma ◽  
Laith Alzubaidi

Recently, several techniques have been developed for vegetable and fruit maturing recognition. Adding hardware designs will enhance the recognition performance. Especially, parallel processing designs efficiently speed up the process functions. This paper utilizes a hardware parallel processing design called field programmable gate array for that purpose. In addition, two different methods; namely K-means clustering and color thresholding are used for recognizing the apple maturation. This study aims to design and implement a mature apple recognition system based on field programmable gate array. The results demonstrate that the color thresholding technique is faster, more reliable and more effective than the K-means clustering technique.

Steganography is one of the commanding and commonly used methods for embedding data. Realizing steganography in hardware supports to speed up steganography. This work realizesthe novel approach for generation of Key, for hiding and encoding processes of image steganography using LSB and HAAR DWT.The data embedding process is realized with seven segment display pattern as a secret key with various sizes using HAAR DWT and LSB. Maximum hiding effectiveness is also attained from this work. The same is implemented in hardware using reconfigurable device Field programmable gate array to improve the speed, area and power. The proposed work is also evaluated improved PSNR using MATLAB.


Author(s):  
PRASHANTH M. ULLAGADDI ◽  
K. N. PUSHPALATHA ◽  
ARAVIND KUMAR GAUTAM

Iris recognition is an automated method of biometric identification that uses mathematical pattern-recognition techniques on video images of the irises of an individual’s eyes, whose complex random patterns are unique and can be seen from some distance. Modern iris recognition algorithms can be computationally intensive, yet are designed for traditional sequential processing elements, such as a personal computer. However, a parallel processing alternative using Field Programmable Gate Array offers an opportunity to speed up iris recognition. Within the means of this project, iris template generation with directional filtering, which is a computationally expensive, yet parallel portion of a modern iris recognition algorithm, is parallelized on an FPGA system. An algorithm that is both accurate and fast in a hardware design that is small and transportable are crucial to the implementation of this tool. As part of an ongoing effort to meet these criteria, this method improves a iris recognition algorithm, namely pupil isolation. A significant speed-up of pupil isolation by implementing this portion of the algorithm on a Field Programmable Gate Array.


2008 ◽  
Author(s):  
Michael Wirthlin ◽  
Brent Nelson ◽  
Brad Hutchings ◽  
Peter Athanas ◽  
Shawn Bohner

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