High Speed Publication Subscription Brokering Through Highly Parallel Processing on Field Programmable Gate Array (FPGA)

2010 ◽  
Author(s):  
Chun-Shin Lin
Keyword(s):  
Parallel Processing ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Field Programmable ◽  
Gate Array

High Speed FPGA Based 128-bit Advance Encryption Standard (AES)

2021 ◽  
Vol 11 ◽  
Author(s):  
Ibrahem M. T. Hamidi ◽  
Farah S. H. Al-aassi
Keyword(s):  
High Throughput ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Design Tool ◽  
Advanced Encryption Standard ◽  
Clock Frequency ◽  
Advance Encryption Standard ◽  
Field Programmable ◽  
Internal Component ◽  
Gate Array

Aim: Achieve high throughput 128 bits FPGA based Advanced Encryption Standard. Background: Field Programmable Gate Array (FPGA) provides an efficient platform for design AES cryptography system. It provides the capability to control over each bit using HDL programming language such as VHDL and Verilog which results an output speed in Gbps rang. Objective: Use Field Programmable Gate Array (FPGA) to design high throughput 128 bits FPGA based Advanced Encryption Standard. Method: Pipelining technique has used to achieve maximum possible speed. The level of pipelining includes round pipelining and internal component pipelining where number of registers inserted in particular places to increase the output speed. The proposed design uses combinatorial logic to implement the byte substitution. The s-box implemented using composed field arithmetic with 7 stages of pipelining to reduce the combinatorial logic level. The presented model has implemented using VHDL in Xilinix ISETM 14.4 design tool. Result: The achieved results were 18.55 Gbps at a clock frequency of 144.96 MHz and area of 1568 Slices in Spartan3 xc3s1000 hardware. Conclusion: The results show that the proposed design reaches a high throughput with acceptable area usage compare with other designs in the literature.

scholarly journals Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

2019 ◽  
Vol 29 (09) ◽  
pp. 2050136
Author(s):  
Yuuki Tanaka ◽  
Yuuki Suzuki ◽  
Shugang Wei
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Number System ◽  
Logic Circuit ◽  
Fpga Implementation ◽  
Number Representation ◽  
Representation System ◽  
Representation Systems ◽  
Field Programmable ◽  
Gate Array

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

A very-high-speed field-programmable gate array using metal-to-metal antifuse programmable elements

1992 ◽  
Vol 23 (7) ◽  
pp. 561-568 ◽  
Author(s):  
J. Birkner ◽  
A. Chan ◽  
H.T. Chua ◽  
A. Chao ◽  
K. Gordon ◽  
...  
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Field Programmable ◽  
Gate Array ◽  
Very High

scholarly journals High-speed endless optical polarization stabilization using calibrated waveplates and field-programmable gate array-based digital controller

2008 ◽  
Vol 16 (23) ◽  
pp. 18984 ◽  
Author(s):  
Ariya Hidayat ◽  
Benjamin Koch ◽  
Hongbin Zhang ◽  
Vitali Mirvoda ◽  
Manfred Lichtinger ◽  
...  
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Digital Controller ◽  
Optical Polarization ◽  
Field Programmable ◽  
Gate Array

High Speed Matrix Multiplication Implementation Using Field Programmable Gate Array

2014 ◽  
Vol 7 (2) ◽  
pp. 75-78 ◽  
Author(s):  
Shriyashi Jain ◽  
◽  
Neeraj Kumar ◽  
Jaikaran Singh ◽  
Mukesh Tiwari
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Matrix Multiplication ◽  
Field Programmable ◽  
Gate Array

Application of FPGAs to High-Speed Condition Based Maintenance of Rolling Element Bearings

Volume 3 ◽  
2004 ◽  
Author(s):  
Mark Harriman ◽  
Farbod Zorriassatine ◽  
Rob Parkin ◽  
Mike Jackson ◽  
Jo Coy
Keyword(s):  
Signal Processing ◽  
Condition Monitoring ◽  
Execution Time ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Mechanical Engineering ◽  
Electronic Engineering ◽  
Bearing Condition Monitoring ◽  
Field Programmable ◽  
Gate Array

Field-Programmable Gate Array (FPGA) technology has been applied widely in electronic engineering and computing industries, but it has not had the same level of reception in other disciplines including mechanical engineering [1]. The purpose of this paper is to examine FPGA implementations of signal processing techniques that are used in the context of bearing condition monitoring. As the number of bearings can be large sparse sensor arrays are used to locate and detect their condition. The demands of realtime process monitoring [2] [3] can place a heavy burden upon the monitoring system. Field-Programmable Gate Array (FPGA) technology [4] in this application makes it possible to implement more sophisticated algorithms. These exploit its high-speed, parallel, reconfigurable architecture. Bring forth the advantages of FPGA technology to condition monitoring. The techniques covered are: cross-correlation, digital signal processing (DSP) Infinite Impulse Response (IIR) filters, neural networks and signature matching. The implemented designs are optimised for both execution time and the amount of logic area consumed. Results were obtained from each technique and were assessed and compared in terms of execution time and also the amount of logic consumed on the FPGA. Over the past 15 years FPGA technology has been applied extensively in electronic engineering but its scope has not been as vastly in mechanical engineering. The objective of this paper was to examine an application in mechanical engineering. Ideally this would be done with a mechanical engineering compatible approach, giving rise to a methodology, which would allow FPGA programming [5] to become a transferable skill.

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