scholarly journals Solar-Blind Focal Plane Array Photodetectors for Massive Parallel Processing Application Based on Optoelectronic Integrated Circuit and Field-Programmable Gate Array

2015 ◽  
Author(s):  
Hary Oktavianto ◽  
Keisuke Yamane ◽  
Hiroto Sekiguchi ◽  
Akihiro Wakahara
Keyword(s):  
Parallel Processing ◽  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
Focal Plane ◽  
Focal Plane Array ◽  
Processing Application ◽  
Solar Blind ◽  
Field Programmable ◽  
Gate Array ◽  
Massive Parallel Processing

scholarly journals Enhancing Apple Maturation Recognition Performance Based on Field Programmable Gate Array Implementation

2019 ◽  
Vol 54 (6) ◽  
Author(s):  
Fouad H. Awad ◽  
Mohammed A. Fadhel ◽  
Khattab M. Ali Alheeti ◽  
Omran Al-Shamma ◽  
Laith Alzubaidi
Keyword(s):  
Parallel Processing ◽  
Field Programmable Gate Array ◽  
Recognition Performance ◽  
Recognition System ◽  
Clustering Technique ◽  
Field Programmable ◽  
Speed Up ◽  
Gate Array ◽  
Hardware Designs ◽  
Mature Apple

Recently, several techniques have been developed for vegetable and fruit maturing recognition. Adding hardware designs will enhance the recognition performance. Especially, parallel processing designs efficiently speed up the process functions. This paper utilizes a hardware parallel processing design called field programmable gate array for that purpose. In addition, two different methods; namely K-means clustering and color thresholding are used for recognizing the apple maturation. This study aims to design and implement a mature apple recognition system based on field programmable gate array. The results demonstrate that the color thresholding technique is faster, more reliable and more effective than the K-means clustering technique.

scholarly journals InSight: An FPGA-Based Neuromorphic Computing System for Deep Neural Networks

2020 ◽  
Vol 10 (4) ◽  
pp. 36
Author(s):  
Taeyang Hong ◽  
Yongshin Kang ◽  
Jaeyong Chung
Keyword(s):  
Neural Networks ◽  
Image Classification ◽  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
Deep Neural Networks ◽  
Computing System ◽  
Neuromorphic Computing ◽  
Neuromorphic Hardware ◽  
Field Programmable ◽  
Gate Array

Deep neural networks have demonstrated impressive results in various cognitive tasks such as object detection and image classification. This paper describes a neuromorphic computing system that is designed from the ground up for energy-efficient evaluation of deep neural networks. The computing system consists of a non-conventional compiler, a neuromorphic hardware architecture, and a space-efficient microarchitecture that leverages existing integrated circuit design methodologies. The compiler takes a trained, feedforward network as input, compresses the weights linearly, and generates a time delay neural network reducing the number of connections significantly. The connections and units in the simplified network are mapped to silicon synapses and neurons. We demonstrate an implementation of the neuromorphic computing system based on a field-programmable gate array that performs image classification on the hand-wirtten 0 to 9 digits MNIST dataset with 99.37% accuracy consuming only 93uJ per image. For image classification on the colour images in 10 classes CIFAR-10 dataset, it achieves 83.43% accuracy at more than 11× higher energy-efficiency compared to a recent field-programmable gate array (FPGA)-based accelerator.

From Simulation to FPGA Control Circuit Implementation for Wind Power with Battery Charging

2012 ◽  
Vol 588-589 ◽  
pp. 777-780
Author(s):  
Cheng Shion Shieh
Keyword(s):  
Wind Power ◽  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Flow Chart ◽  
Charging Control ◽  
Field Programmable ◽  
Hardware Description ◽  
Fpga Chip ◽  
Gate Array

While application of field-programmable gate array (FPGA) chip has been extensively investigated, the charging control is relatively unexplored. This paper proposes a flow chart of energy storage for wind power system with Lead-Acid battery whose charging control is constructed by Very High Speed Integrated Circuit Hardware Description Language (VHDL) code. This research focuses on the proposed digital control algorithm can be directly downloaded into field-programmable gate array (FPGA) chip after simulation finishing. This saves greatly time on hardware circuit design. A simulation is presented to illustrate the effectiveness of the proposed charging flow chart.

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