scholarly journals Cause analysis of width-dependence of on-current variability in thin gate-all-around silicon nanowire MOSFET

Author(s):  
Zihao Liu ◽  
Tomoko Mizutani ◽  
Takuya Saraya ◽  
Masaharu Kobayashi ◽  
Toshiro HIRAMOTO

Abstract In this study, the width dependence of on-current variability in extremely narrow gate-all-around (GAA) silicon nanowire MOSFET down to 2nm width is analyzed by variability decomposition into components as well as analyzing the Pelgrom plot. It is found that the current variability rapidly increases below 4nm mainly due to quantum-effect-induced threshold voltage variability and silicon-thickness-fluctuation-induced mobility fluctuation (μfluctuation). The current variability becomes even worse in 2nm, which is fundamentally caused by line width roughness.

Open Physics ◽  
2011 ◽  
Vol 9 (2) ◽  
Author(s):  
Esmaeil Dastjerdy ◽  
Rahim Ghayour ◽  
Hojjat Sarvari

AbstractIn order to investigate the specifications of nanoscale transistors, we have used a three dimensional (3D) quantum mechanical approach to simulate square cross section silicon nanowire (SNW) MOSFETs. A three dimensional simulation of silicon nanowire MOSFET based on self consistent solution of Poisson-Schrödinger equations is implemented. The quantum mechanical transport model of this work uses the non-equilibrium Green’s function (NEGF) formalism. First, we simulate a double-gate (DG) silicon nanowire MOSFET and compare the results with those obtained from nanoMOS simulation. We understand that when the transverse dimension of a DG nanowire is reduced to a few nanometers, quantum confinement in that direction becomes important and 3D Schrödinger equation must be solved. Second, we simulate gate-all-around (GAA) silicon nanowire MOSFETs with different shapes of gate. We have investigated GAA-SNW-MOSFET with an octagonal gate around the wire and found out it is more suitable than a conventional GAA MOSFET for its more I on/I off, less Drain-Induced-Barrier-Lowering (DIBL) and less subthreshold slope.


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