scholarly journals Smart Fast Motion Estimation Processors

2019 ◽  
Vol 8 (9S3) ◽  
pp. 929-935
Keyword(s):  
Data Transfer ◽  
Video Quality ◽  
General Purpose ◽  
Video Codec ◽  
Fast Motion Estimation ◽  
Video Broadcasting ◽  
General Purpose Processor ◽  
High Data ◽  
Fast Motion ◽  
Best Execution

This Paper displays an adaptable and versatile movement estimation processor fit for supporting the handling prerequisites for top notch (HD) video utilizing the H.264 Advanced Video Codec, which is appropriate for FPGA execution. This paper dependent on General Purpose processor plan for movement estimation process. Quick movement estimation calculation with full pursuit calculation and precious stone hunt calculation. Where the two calculations have been executed in a solitary processor. So client can powerfully pick as per best execution. A client can choose the alternative of video quality at run time. In contrast to most past work, our center is enhanced to execute all current quick square coordinating calculations, to coordinate or surpass the between casing expectation execution of full-seek approaches at the HD goals generally being used today. Different tale movement estimation designs have been proposed all through the writing for dealing with the high data transfer capacity imperative nature of Video Broadcasting. A High precision full pursuit fixed square inquiry calculation is used to lessen the general transmission capacity and power prerequisite for transmitting live video arrangements. Despite the fact that full hunt guarantees high exactness, it tradeoffs its calculation time for precision. So the precision advantage is emphatically obscured by working velocity. To supplant the Full inquiry calculation another Modified Diamond seek calculation has been proposed with best precision and streamlined movement estimation length. Execution assessment of FBS Full hunt and Diamond look will be thought about for future investigation

scholarly journals A Dynamic and Highly Configurable Crypto-Processor for brief communication interval

2021 ◽  
Vol 23 (05) ◽  
pp. 551-561
Author(s):  
Riya Bagul ◽  
◽  
Atharva Karaguppi ◽  
Vishwas Karale ◽  
Mudit Singal ◽  
...  
Keyword(s):  
Data Security ◽  
Data Exchange ◽  
Short Communication ◽  
Data Transfer ◽  
Data Encryption ◽  
General Purpose ◽  
Security Measures ◽  
Computing Systems ◽  
General Purpose Processor ◽  
Innovative Methodology

In modern computing systems data security is of paramount importance. The data transfer must be made secure because it can be significantly sensitive for any organization involved. This paper expounds a SOC architecture to facilitate end to end secure data exchange for applications involving short communication intervals. This SOC has been designed to behave as a co-processor which along with a standard general-purpose processor would serve as a cryptosystem. The SOC employs two famous algorithms – RSA and AES for cryptography. In contrast to usual single key cryptographic systems, this paper tries to elaborate an innovative methodology involving dynamic security measures that makes the system distributed rather than making it central to a specific algorithm and hence a particular key. The methodology involves generating and using an AES key for data encryption and RSA key for secure transfer of the AES key between the point of transmission and reception.

scholarly journals On the Performance of Self-Concatenated Coding for Wireless Mobile Video Transmission Using DSTS-SP-Assisted Smart Antenna System

2021 ◽  
Vol 2021 ◽  
pp. 1-10
Author(s):  
Nasru Minallah ◽  
Ishtiaque Ahmed ◽  
Muhammad Ijaz ◽  
Atif Sardar Khan ◽  
Laiq Hasan ◽  
...  
Keyword(s):  
Iterative Decoding ◽  
Information Transfer ◽  
Video Transmission ◽  
Smart Antenna ◽  
Video Quality ◽  
Sphere Packing ◽  
Antenna System ◽  
Video Codec ◽  
Extrinsic Information ◽  
High Data

In the current age of advanced technologies, there is an escalating demand for reliable wireless systems, catering to the high data rates of mobile multimedia applications. This article presents a novel approach to the concept of Self-Concatenated Convolutional Coding (SECCC) with Sphere Packing (SP) modulation via Differential Space-Time Spreading- (DSTS-) based smart antennas. The two transmitters provide transmit diversity which is capable of recuperating the signal from the effects of fading, even with a single receiving antenna. The proposed DSTS-SP SECCC scheme is probed for the Rayleigh fading channel. The SECCC structure is developed using the Recursive Systematic Convolutional (RSC) code with the aid of an interleaver. Interleaving generates randomness in exchange for extrinsic information between the constituent decoders. Iterative decoding is invoked at the receiving side to enhance the output performance by attaining fruitful convergence. The convergence behaviour of the proposed system is investigated using EXtrinsic Information Transfer (EXIT) curves. The performance of the proposed system is ascertained with the H.264 standard video codec. The perceived video quality of DSTS-SP SECCC is found to be significantly better than that of the DSTS-SP RSC. To be more precise, the proposed DSTS-SP SECCC system exhibits an E b / N 0 gain of 8 dB at the PSNR degradation point of 1 dB, relative to the equivalent rate DSTS-SP RSC. Similarly, an E b / N 0 gain of 10 dB exists for the DSTS-SP SECCC system at 1 dB degradation point when compared with the SECCC scheme dispensing with the DSTS-SP approach.

scholarly journals DMPDS: A Fast Motion Estimation Algorithm Targeting High Resolution Videos and Its FPGA Implementation

2012 ◽  
Vol 2012 ◽  
pp. 1-12 ◽  
Author(s):  
Gustavo Sanchez ◽  
Felipe Sampaio ◽  
Marcelo Porto ◽  
Sergio Bampi ◽  
Luciano Agostini
Keyword(s):  
High Resolution ◽  
Motion Estimation ◽  
Real Time ◽  
Video Quality ◽  
Estimation Algorithm ◽  
High Definition ◽  
Fast Motion Estimation ◽  
Processing Rate ◽  
Diamond Search ◽  
Fast Motion

This paper presents a new fast motion estimation (ME) algorithm targeting high resolution digital videos and its efficient hardware architecture design. The new Dynamic Multipoint Diamond Search (DMPDS) algorithm is a fast algorithm which increases the ME quality when compared with other fast ME algorithms. The DMPDS achieves a better digital video quality reducing the occurrence of local minima falls, especially in high definition videos. The quality results show that the DMPDS is able to reach an average PSNR gain of 1.85 dB when compared with the well-known Diamond Search (DS) algorithm. When compared to the optimum results generated by the Full Search (FS) algorithm the DMPDS shows a lose of only 1.03 dB in the PSNR. On the other hand, the DMPDS reached a complexity reduction higher than 45 times when compared to FS. The quality gains related to DS caused an expected increase in the DMPDS complexity which uses 6.4-times more calculations than DS. The DMPDS architecture was designed focused on high performance and low cost, targeting to process Quad Full High Definition (QFHD) videos in real time (30 frames per second). The architecture was described in VHDL and synthesized to Altera Stratix 4 and Xilinx Virtex 5 FPGAs. The synthesis results show that the architecture is able to achieve processing rates higher than 53 QFHD fps, reaching the real-time requirements. The DMPDS architecture achieved the highest processing rate when compared to related works in the literature. This high processing rate was obtained designing an architecture with a high operation frequency and low numbers of cycles necessary to process each block.

Design and Implementation of Low Energy Wireless Network Nodes based on Hardware Compression Acceleration

2019 ◽  
Vol 12 ◽  
Author(s):  
Hui Yang ◽  
Anand Nayyar
Keyword(s):  
Energy Consumption ◽  
Data Compression ◽  
Energy Saving ◽  
Optimization Design ◽  
Hardware Acceleration ◽  
Transmission Efficiency ◽  
General Purpose ◽  
Storage Space ◽  
General Purpose Processor ◽  
Compression Time

: In the fast development of information, the information data is increasing in geometric multiples, and the speed of information transmission and storage space are required to be higher. In order to reduce the use of storage space and further improve the transmission efficiency of data, data need to be compressed. processing. In the process of data compression, it is very important to ensure the lossless nature of data, and lossless data compression algorithms appear. The gradual optimization design of the algorithm can often achieve the energy-saving optimization of data compression. Similarly, The effect of energy saving can also be obtained by improving the hardware structure of node. In this paper, a new structure is designed for sensor node, which adopts hardware acceleration, and the data compression module is separated from the node microprocessor.On the basis of the ASIC design of the algorithm, by introducing hardware acceleration, the energy consumption of the compressed data was successfully reduced, and the proportion of energy consumption and compression time saved by the general-purpose processor was as high as 98.4 % and 95.8 %, respectively. It greatly reduces the compression time and energy consumption.

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