scholarly journals An Energy Efficient Binary Magnitude Comparator for Nanotechnology Applications

2020 ◽  
Vol 8 (6) ◽  
pp. 430-436
Keyword(s):  
Energy Dissipation ◽  
Cellular Automata ◽  
Power Consumption ◽  
Power Dissipation ◽  
Energy Efficient ◽  
Cmos Technology ◽  
The Other ◽  
Cycle Performance ◽  
Quantum Dot Cellular Automata ◽  
Cell Numbers

Quantum-dot cellular automata (QCA) is inventive nanotechnology that suggest lesser size, lesser power consumption, with more rapid speeds and deliberated as a clarification to the scaling difficulties with CMOS technology. Physical bounds of CMOS for instance the effects of quantum and the limits of technologies like power dissipation obstruct the motion of microelectronics using consistent circuit scaling. In this paper, a 1-bit binary magnitude comparator circuit is proposed that takes down the count of QCA cells related to the previously reported design’s cell numbers. The proposed course of study involves just around 29 % of the total area as compared to the preceding design with the lesser speed and clocking cycle performance and energy dissipation also. QCA designerE tool is used for simulation and finding the parameters also. The projected magnitude comparator also compares the metrics result with some of the other preceeding patterns.

Energy Efficient Configurable Layout of Logic Block in QCA frame work for an FPGA

2020 ◽  
Vol 12 ◽  
Author(s):  
Arindam Sadhu ◽  
Rimpa Dey Sarkar ◽  
Kunal Das ◽  
Debashis De ◽  
Maitreyi Ray Kanjilal
Keyword(s):  
Energy Dissipation ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Embedded System ◽  
Power Dissipation ◽  
Energy Efficient ◽  
Average Energy ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Logic Block

Aims: Embedded system plays a vital role in today’s life. Hence our motivation is concentrated on area-delay-energy efficient embedded system design in post-CMOS technology i.e. QCA. Objectives: The research is focused on area-delay-energy efficient configurable logic block (CLB) design for field programmable gate array architecture (FPGA) with successful simulation based on a next generation technology, Quantum-dot cellular automata. Methodology: Each proposed circuits are designed in post CMOS 4 dot 2 electron technology i.e. QCA(Quantum Dot Cellular Automata) which has been adopted in circuit implementation due to Low power dissipation, high clock frequency and high package density. Functionality of every circuit is verified by QCADesigner. QCAPro tool is used for power dissipation measurement. Results: In contrast a new approach of using de-multiplexer replacing the decoder has been introduced which results in reduction of the average energy dissipation almost 57%. A NOR based D flip-flop memory architecture and multiplexer is also used in the look up table for the configurable logic block. The proposed architecture thus reduces the overall latency. Proposed CLB is consists of 6356 number of QCA cell with covering 7.44 um2 area. Write and read latency of proposed CLB is 12 and 7.25 QCA clock respectively. Conclusion: The presented paper concludes those read and write latency reduction occurs; average energy dissipation, leakage and switching energy dissipation has been reduced massively and ensues an advantage of overall reduction of the latency for the proposed CLB in the process.

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

scholarly journals Nanosensor Data Processor in Quantum-Dot Cellular Automata

2014 ◽  
Vol 2014 ◽  
pp. 1-14 ◽  
Author(s):  
Fenghui Yao ◽  
Mohamed Saleh Zein-Sabatto ◽  
Guifeng Shao ◽  
Mohammad Bodruzzaman ◽  
Mohan Malkani
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Consumption ◽  
Input Data ◽  
Cmos Technology ◽  
Sigmoid Function ◽  
Lower Power ◽  
Quantum Dot Cellular Automata ◽  
Data Processor ◽  
High Level

Quantum-dot cellular automata (QCA) is an attractive nanotechnology with the potential alterative to CMOS technology. QCA provides an interesting paradigm for faster speed, smaller size, and lower power consumption in comparison to transistor-based technology, in both communication and computation. This paper describes the design of a 4-bit multifunction nanosensor data processor (NSDP). The functions of NSDP contain (i) sending the preprocessed raw data to high-level processor, (ii) counting the number of the active majority gates, and (iii) generating the approximate sigmoid function. The whole system is designed and simulated with several different input data.

An Ultra-Low-Power Five-Input Majority Gate in Quantum-Dot Cellular Automata

2020 ◽  
Vol 29 (11) ◽  
pp. 2050176
Author(s):  
Feifei Deng ◽  
Guangjun Xie ◽  
Shaowei Wang ◽  
Xin Cheng ◽  
Yongqiang Zhang
Keyword(s):  
Cellular Automata ◽  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Single Layer ◽  
Full Adder ◽  
Majority Gate ◽  
Ultra Low Power ◽  
Quantum Dot Cellular Automata ◽  
Number Of Cells

Quantum-dot cellular automata (QCA) is a highly attractive alternative to CMOS for future digital circuit design, relying on its high-performance and low-power-consumption features. This paper analyzes and compares previously published five-input majority gates. These designs do not perform well in terms of physical properties, especially concerting power consumption. Therefore, an ultra-low-power five-input majority gate in one layer is proposed, which uses a minimum number of cells and smaller area, and achieves the expected highly polarized output compared with previous designs. In order to evaluate its practicability, a new one-bit coplanar full-adder is proposed. The analysis results show that this full-adder performs well compared with existing multilayer and single-layer designs. The number of cells of the proposed design is reduced by 7.14% to get the same area and clock delay compared with the best coplanar full-adder. In addition, its power dissipation is also reduced by 9.28% at 0.5[Formula: see text], 11.09% at 1[Formula: see text] and 12.66% at 1.5[Formula: see text] in terms of average energy dissipation compared with the best single-layer design. QCADesigner tool is used to verify the simulation results of the proposed designs and QCAPro tool is used to evaluate the power dissipation of all considered designs.

scholarly journals An Energy Efficient Quantum-dot Cellular Automata Design of 1/2 and 1/3 Convolution Encoder

2021 ◽  
Author(s):  
Rahil Jahangir ◽  
Mohammad Mudakir Fazili ◽  
Neeraj Tripathi
Keyword(s):  
Energy Dissipation ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Energy Efficient ◽  
High Speed ◽  
Fault Tolerant ◽  
Device Fabrication ◽  
Design Parameters ◽  
Fabrication Technology ◽  
Quantum Dot Cellular Automata

Abstract Quantum-dot cellular automata (QCA) technology is considered to be the future of nanoelectronic device fabrication technology. The fabrication density of the transistors in a particular area in the current nanoelectronic industry has saturated. Adroit alternate to current CMOS based VLSI technology is being researched upon. QCA technology is considered to be the noblest post-CMOS era fabrication technology. In this paper, novel energy-efficient QCA designs for 1/2 and 1/3 convolution encoders have been presented. Both the presented designs were proven to be efficient than previously designed circuits. The efficiency of the design is calculated for critical design parameters like cell count, cell area, latency (clock phases), complexity and energy dissipation. The proposed 1/2 convolution encoder uses 21 QCA cells consuming an area of 0.012µm2. The complexity of this design was calculated to be 2. The energy dissipation analysis revealed that the presented circuit dissipated 14.03meV of energy. The proposed 1/3 convolution encoder uses 32 QCA cells consuming an area of 0.025µm2. The energy dissipation analysis revealed that the presented circuit dissipated 16.88meV of energy. Both the proposed designs used only a few more extra cells than the previously designed circuits but induced stronger polarizations and were more fault-tolerant. It was found that the circuits proposed are 25% more energy efficient than previously designed circuits. The latency of the proposed designs was of 2 clock phases, thus making it suitable for high-speed operation. Significant improvement of the designs was done to optimize the circuit for secure nano-communication devices.

A Novel Enhanced-Majority-Voter Universal Gate in Quantum Dot Cellular Automata with Energy Dissipation Analysis

2017 ◽  
Vol 9 (3) ◽  
pp. 03034-1-03034-7 ◽  
Author(s):  
S. Umira ◽  
◽  
R. Qadri ◽  
Z. A. Bangi ◽  
M. Tariq Banday ◽  
...  
Keyword(s):  
Energy Dissipation ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Quantum Dot Cellular Automata ◽  
Majority Voter ◽  
Universal Gate

Toward Efficient Design of Flip-flops in Quantum-Dot Cellular Automata with Power Dissipation Analysis

2018 ◽  
Vol 57 (11) ◽  
pp. 3419-3428 ◽  
Author(s):  
Ali Newaz Bahar ◽  
Radhouane Laajimi ◽  
Md. Abdullah-Al-Shafi ◽  
Kawsar Ahmed
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Efficient Design ◽  
Quantum Dot Cellular Automata
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