Reducing the effect of crosstalk noise from defocused multi-depth holographic image with a rasterize encoding method

Author(s):  
Siao-Ting Li ◽  
Chih-Hao Chuang ◽  
Chung Feng Kuo ◽  
Hoang-Yan Lin ◽  
Chin-I Huang ◽  
...  
Author(s):  
Siao-Ting Li ◽  
Chih-Hao Chuang ◽  
Chung Feng Kuo ◽  
Hoang-Yan Lin ◽  
Chin-I Huang ◽  
...  

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Kuang Tsan Lin ◽  
Sheng Lih Yeh

The Rivest-Shamir-Adleman (RSA) encryption method and the binary encoding method are assembled to form a hybrid hiding method to hide a covert digital image into a dot-matrix holographic image. First, the RSA encryption method is used to transform the covert image to form a RSA encryption data string. Then, all the elements of the RSA encryption data string are transferred into binary data. Finally, the binary data are encoded into the dot-matrix holographic image. The pixels of the dot-matrix holographic image contain seven groups of codes used for reconstructing the covert image. The seven groups of codes are identification codes, covert-image dimension codes, covert-image graylevel codes, pre-RSA bit number codes, RSA key codes, post-RSA bit number codes, and information codes. The reconstructed covert image derived from the dot-matrix holographic image and the original covert image are exactly the same.


MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 49-54 ◽  
Author(s):  
E. Todd Ryan ◽  
Andrew J. McKerrow ◽  
Jihperng Leu ◽  
Paul S. Ho

Continuing improvement in device density and performance has significantly affected the dimensions and complexity of the wiring structure for on-chip interconnects. These enhancements have led to a reduction in the wiring pitch and an increase in the number of wiring levels to fulfill demands for density and performance improvements. As device dimensions shrink to less than 0.25 μm, the propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant. Accordingly the interconnect delay now constitutes a major fraction of the total delay limiting the overall chip performance. Equally important is the processing complexity due to an increase in the number of wiring levels. This inevitably drives cost up by lowering the manufacturing yield due to an increase in defects and processing complexity.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILDs) and alternative architectures have surfaced to replace the current Al(Cu)/SiO2 interconnect technology. These alternative architectures will require the introduction of low-dielectric-constant k materials as the interlayer dielectrics and/or low-resistivity conductors such as copper. The electrical and thermomechanical properties of SiO2 are ideal for ILD applications, and a change to material with different properties has important process-integration implications. To facilitate the choice of an alternative ILD, it is necessary to establish general criterion for evaluating thin-film properties of candidate low-k materials, which can be later correlated with process-integration problems.


MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 19-27 ◽  
Author(s):  
Wei William Lee ◽  
Paul S. Ho

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.


2020 ◽  
Vol 2020 (17) ◽  
pp. 34-1-34-7
Author(s):  
Matthew G. Finley ◽  
Tyler Bell

This paper presents a novel method for accurately encoding 3D range geometry within the color channels of a 2D RGB image that allows the encoding frequency—and therefore the encoding precision—to be uniquely determined for each coordinate. The proposed method can thus be used to balance between encoding precision and file size by encoding geometry along a normal distribution; encoding more precisely where the density of data is high and less precisely where the density is low. Alternative distributions may be followed to produce encodings optimized for specific applications. In general, the nature of the proposed encoding method is such that the precision of each point can be freely controlled or derived from an arbitrary distribution, ideally enabling this method for use within a wide range of applications.


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