Implementation of Improved Hash and Mapping Modified Low Power Parallel Bloom Filter Design

2013 ◽  
Vol 7 (4) ◽  
pp. 11-21
Author(s):  
K. Saravanan ◽  
A. Senthilkumar
Keyword(s):  
Low Power ◽  
False Positive ◽  
Filter Design ◽  
Parallel Architecture ◽  
Bloom Filter ◽  
Bloom Filters ◽  
Positive Ratio ◽  
False Positive Ratio ◽  
Field Programmable ◽  
Mapping Scheme

In this article, the authors present an investigation on bloom filters and introduce a new improved variant, which uses a secure modified hash function and suggested improved mapping scheme with an efficient parallel architecture. This novel architecture provides efficient, relatively fast membership querying and compact information representation with negligible false positive. This is relatively a low power and secure design with very less false positive ratio when compared with the traditional bloom filters. The design has been evaluated and tested using Xilinx 65 nm Virtex-5 field-programmable gate array as the target technology. The performance matrices are false positive ratio, power, speed and compactness.

scholarly journals A Novel Prefix Cache with Two-Level Bloom Filters in IP Address Lookup

2020 ◽  
Vol 10 (20) ◽  
pp. 7198
Author(s):  
Junghwan Kim ◽  
Myeong-Cheol Ko ◽  
Moon Sun Shin ◽  
Jinsoo Kim
Keyword(s):  
False Positive ◽  
Bloom Filter ◽  
Bloom Filters ◽  
Experimental Result ◽  
Ip Address ◽  
Positive Ratio ◽  
Ip Addresses ◽  
False Positive Ratio ◽  
Ip Address Lookup ◽  
Filter Size

Prefix caching is one of the notable techniques in enhancing the IP address lookup performance which is crucial in packet forwarding. A cached prefix can match a range of IP addresses, so prefix caching leads to a higher cache hit ratio than IP address caching. However, prefix caching has an issue to be resolved. When a prefix is matched in a cache, the prefix cannot be the result without assuring that there is no longer descendant prefix of the matching prefix which is not cached yet. This is due to the aspect of the IP address lookup seeking to find the longest matching prefix. Some prefix expansion techniques avoid the problem, but the expanded prefixes occupy more entries as well as cover a smaller range of IP addresses. This paper proposes a novel prefix caching scheme in which the original prefix can be cached without expansion. In this scheme, for each prefix, a Bloom filter is constructed to be used for testing if there is any matchable descendant. The false positive ratio of a Bloom filter generally grows as the number of elements contained in the filter increases. We devise an elaborate two-level Bloom filter scheme which adjusts the filter size at each level, to reduce the false positive ratio, according to the number of contained elements. The experimental result shows that the proposed scheme achieves a very low cache miss ratio without increasing the number of prefixes. In addition, most of the filter assertions are negative, which means the proposed prefix cache effectively hits the matching prefix using the filter.

scholarly journals Bloom Filter-Based Parallel Architecture for Accelerating Equi-Join Operation on FPGA

Electronics ◽  
2021 ◽  
Vol 10 (15) ◽  
pp. 1778
Author(s):  
Binhao He ◽  
Meiting Xue ◽  
Shubiao Liu ◽  
Wei Luo
Keyword(s):  
Relational Databases ◽  
Parallel Architecture ◽  
Operation Time ◽  
Bloom Filter ◽  
Search Tree ◽  
Binary Search Tree ◽  
Maximum Acceleration ◽  
Data Intensive ◽  
Match Rate ◽  
Field Programmable

As one of the most important operations in relational databases, the join is data-intensive and time-consuming. Thus, offloading this operation using field-programmable gate arrays (FPGAs) has attracted much interest and has been broadly researched in recent years. However, the available SRAM-based join architectures are often resource-intensive, power-consuming, or low-throughput. Besides, a lower match rate does not lead to a shorter operation time. To address these issues, a Bloom filter (BF)-based parallel join architecture is presented in this paper. This architecture first leverages the BF to discard the tuples that are not in the join result and classifies the remaining tuples into different channels. Second, a binary search tree is used to reduce the number of comparisons. The proposed method was implemented on a Xilinx FPGA, and the experimental results show that under a match rate of 50%, our architecture achieved a high join throughput of 145.8 million tuples per second and a maximum acceleration factor of 2.3 compared to the existing SRAM-based join architectures.

scholarly journals Optimal False-Positive-Free Bloom Filter Design for Scalable Multicast Forwarding

2015 ◽  
Vol 23 (6) ◽  
pp. 1832-1845 ◽  
Author(s):  
Janos Tapolcai ◽  
Jozsef Biro ◽  
Peter Babarczi ◽  
Andras Gulyas ◽  
Zalan Heszberger ◽  
...  
Keyword(s):  
False Positive ◽  
Filter Design ◽  
Bloom Filter ◽  
Multicast Forwarding

scholarly journals Quality Assessment of Tire Shearography Images via Ensemble Hybrid Faster Region-Based ConvNets

Electronics ◽  
2019 ◽  
Vol 9 (1) ◽  
pp. 45 ◽  
Author(s):  
Chuan-Yu Chang ◽  
Kathiravan Srinivasan ◽  
Wei-Chun Wang ◽  
Ganapathy Pattukandan Ganapathy ◽  
Durai Raj Vincent ◽  
...  
Keyword(s):  
Neural Networks ◽  
Quality Assessment ◽  
Convolutional Neural Networks ◽  
False Positive ◽  
High Performance ◽  
Learning Approaches ◽  
Positive Ratio ◽  
False Positive Ratio ◽  
Proposed Model ◽  
Human Eyes

In recent times, the application of enabling technologies such as digital shearography combined with deep learning approaches in the smart quality assessment of tires, which leads to intelligent tire manufacturing practices with automated defects detection. Digital shearography is a prominent approach that can be employed for identifying the defects in tires, usually not visible to human eyes. In this research, the bubble defects in tire shearography images are detected using a unique ensemble hybrid amalgamation of the convolutional neural networks/ConvNets with high-performance Faster Region-based convolutional neural networks. It can be noticed that the routine of region-proposal generation along with object detection is accomplished using the ConvNets. Primarily, the sliding window based ConvNets are utilized in the proposed model for dividing the input shearography images into regions, in order to identify the bubble defects. Subsequently, this is followed by implementing the Faster Region-based ConvNets for identifying the bubble defects in the tire shearography images and further, it also helps to minimize the false-positive ratio (sometimes referred to as the false alarm ratio). Moreover, it is evident from the experimental results that the proposed hybrid model offers a cent percent detection of bubble defects in the tire shearography images. Also, it can be witnessed that the false-positive ratio gets minimized to 18 percent.

Limits of the ‘Mini-Mental State’ as a screening test for dementia and delirium among hospital patients

1982 ◽  
Vol 12 (2) ◽  
pp. 397-408 ◽  
Author(s):  
James C. Anthony ◽  
Linda LeResche ◽  
Unaiza Niaz ◽  
Michael R. Von Korff ◽  
Marshal F. Folstein
Keyword(s):  
Mental State ◽  
False Positive ◽  
Mini Mental State Examination ◽  
False Negative ◽  
General Medical Ward ◽  
Positive Ratio ◽  
False Positive Ratio ◽  
Hospital Patients ◽  
Screen Instrument ◽  
State Examination

SynopsisWith a psychiatrist's standardized clinical diagnosis as the criterion, the ‘Mini-Mental State’ Examination (MMSE) was 87% sensitive and 82% specific in detecting dementia and delirium among hospital patients on a general medical ward. The false positive ratio was 39% and the false negative ratio was 5 %. All false positives had less than 9 years of education; many were 60 years of age or older. Performance on specific MMSE items was related to education or age. These findings confirm the MMSE's value as a screen instrument for dementia and delirium when later, more intensive diagnostic enquiry is possible; they reinforce earlier suggestions that the MMSE alone cannot yield a diagnosis for these conditions.

A Hybrid Approach for Accurate BT Traffic Identification

2010 ◽  
Vol 108-111 ◽  
pp. 279-284
Author(s):  
Ru Hui Zhang ◽  
Ye Du ◽  
Xing Wang ◽  
Zhong Lan Yuan
Keyword(s):  
False Positive ◽  
Hybrid Approach ◽  
Transfer Mechanism ◽  
Preliminary Evaluation ◽  
Traffic Identification ◽  
Positive Ratio ◽  
False Positive Ratio ◽  
Information Method ◽  
Flow Information ◽  
Encrypted Traffic

In this paper, a hybrid approach for identifying the traffic running over BitTorrent (BT) protocol is proposed. Besides the conventional port-based and signature-based methods, another two BT-oriented methods dealing with the peer-information and flow-information of BT traffic are also adopted. The peer-information method makes use of the unencrypted peer-transfer mechanism of BT protocol, and the flow-information method focuses on identifying the encrypted traffic, which evades the above three methods, with low false-positive ratio. The preliminary evaluation shows that our hybrid approach is effective and comprehensive for BT traffic identification.

scholarly journals Design of Low Power Architecture for Approximate Parallel Mid-Point Filter

2022 ◽  
Author(s):  
Nelson Kingsley Joel Peter Thiagarajan ◽  
Vijeyakumar K N ◽  
Saravanakumar S
Keyword(s):  
Image Processing ◽  
Low Power ◽  
Filter Design ◽  
Parallel Architecture ◽  
Approximate Computing ◽  
Error Resilient ◽  
Trade Off ◽  
Power Efficient ◽  
Precise Estimation ◽  
Power Delay Product

Abstract Approximate computing is a modern techniques for design of low power efficient arithmetic circuits for portable error resilient applications. In this work, we have proposed a Adaptive Parallel Mid-Point Filter (APMPF) architecture using proposed imprecise Max-Min Estimator (MME)targeting digital image processing. Parallel architecture for the MME can trade-off hardware at the expense of accuracy are proposed and used in the proposed APMPF. In APMPF, we use three level of sorting to estimate the mid-point of 3 x 3 window. Switching based trimmed filter is proposed for precise estimation of the selected window. Experimental Results interms of Area, Power and Delay with 90nm ASIC technology exposed that to the least, Proposed filters demonstrate 7% and 9% Area Delay Product (ADP) and Power Delay Product (PDP) reductions, respectively, compared to precise filter design.

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