OpenMP-Based Approach for High Level C Loops Synthesis

2017 ◽  
Vol 5 (1) ◽  
pp. 1-16
Author(s):  
Emna Kallel ◽  
Yassine Aoudni ◽  
Mohamed Abid
Keyword(s):  
Embedded Systems ◽  
Shared Memory ◽  
Code Generation ◽  
Systems Design ◽  
Parallel Programs ◽  
Abstraction Level ◽  
Automatic Code ◽  
High Level ◽  
Vhdl Code

The complexity of embedded systems design is continuously augmented, due to the increasing quantity of components and distinct functionalities incorporated into a single system. To deal with this situation, abstraction level of projects is incessantly raised. In addition, techniques to accelerate the code production process have appeared. In this context, the automatic code generation is an interesting technique for the embedded systems project. This work presents an automatic VHDL code generation method based on the OpenMP parallel programming specification. In order to synthesize C code for loops into hardware, the authors applied the directives of OpenMP, which specifies portable implementations of shared memory parallel programs. A case study focused on the use of embedded systems for the DCT algorithm is presented in this paper to demonstrate the feasibility of the proposed approach.

Automatic code generation for embedded systems: From UML specifications to VHDL code

2010 ◽  
Author(s):  
Tomas G. Moreira ◽  
Marco A. Wehrmeister ◽  
Carlos E. Pereira ◽  
Jean-Francois Petin ◽  
Eric Levrat
Keyword(s):  
Embedded Systems ◽  
Code Generation ◽  
Automatic Code Generation ◽  
Automatic Code ◽  
Vhdl Code

MADES FP7 EU Project

2014 ◽  
pp. 181-208
Author(s):  
Alessandra Bagnato ◽  
Imran Quadri ◽  
Etienne Brosse ◽  
Andrey Sadovykh ◽  
Leandro Soares Indrusiak ◽  
...  
Keyword(s):  
Code Generation ◽  
Model Verification ◽  
Automatic Code Generation ◽  
Model Driven ◽  
Hand Model ◽  
Model Verification And Validation ◽  
Automatic Code ◽  
Eu Project ◽  
High Level

This chapter presents the EU-funded MADES FP7 project that aims to develop an effective model-driven methodology to improve the current practices in the development of real-time embedded systems for avionics and surveillance industries. MADES developed an effective SysML/MARTE language subset, and a set of new tools and technologies that support high-level design specifications, validation, simulation, and automatic code generation, while integrating aspects such as component re-use. This chapter illustrates the MADES methodology by means of a car collision avoidance system case study; it presents the underlying MADES language, the design phases, and the set of tools supporting on one hand model verification and validation and, on the other hand, automatic code generation, which enables the implementation on execution platforms such as state-of-the-art FPGAs.

UML as Front-End Language for Embedded Systems Design

2010 ◽  
pp. 1-23
Author(s):  
Lisane Brisolara de Brisolara ◽  
Marcio Eduardo Kreutz ◽  
Luigi Carro
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Systems Design ◽  
Design Flow ◽  
Domain Specific ◽  
History Of ◽  
Uml Diagrams ◽  
The Embedded System ◽  
Definition Of

This chapter covers the use of UML as a modeling language for embedded systems design. It introduces the UML language, presenting the history of its definition, its main diagrams and characteristics. Using a case study, we show that using the standard UML with its limitations one is not able to model many important characteristics of embedded systems. For that reason, UML provides extension mechanisms that enable one to extend the language for a given domain, through the definition of profiles covering domain-specific applications. Several profiles have been proposed for the embedded systems domain, and some of those that have been standardized by OMG are presented here. A case study is also used to present MARTE, a new profile specifically proposed for the embedded system domain, enabling designers to model aspects like performance and schedulability. This chapter also presents a discussion about the effort to generate code from UML diagrams and analyses the open issues to the successful use of UML in the whole embedded system design flow.

scholarly journals Evaluating High-Level Models for Real Time Embedded Systems Design

2004 ◽  
pp. 277-286 ◽  
Author(s):  
Lisane Brisolara ◽  
Leandro B. Becker ◽  
Luigi Carro ◽  
Flávio R. Wagner ◽  
Carlos Eduardo Pereira
Keyword(s):  
Embedded Systems ◽  
Real Time ◽  
Systems Design ◽  
High Level

scholarly journals Adaptivity in high-performance embedded systems: a reactive control model for reliable and flexible design

2014 ◽  
Vol 29 (4) ◽  
pp. 433-451
Author(s):  
Huafeng Yu ◽  
Abdoulaye Gamatié ◽  
Éric Rutten ◽  
Jean-Luc Dekeyser
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Code Generation ◽  
High Performance ◽  
Control Model ◽  
Multimedia System ◽  
Reactive Control ◽  
Data Intensive ◽  
On Chip ◽  
Automatic Code

AbstractSystem adaptivity is increasingly demanded in high-performance embedded systems, particularly in multimedia system-on-chip (SoC), owing to growing quality-of-service requirements. This paper presents a reactive control model that has been introduced in Gaspard, our framework dedicated to SoC hardware/software co-design. This model aims at expressing adaptivity as well as reconfigurability in systems performing data-intensive computations. It is generic enough to be used for description in the different parts of an embedded system, for example, specification of how different data-intensive algorithms can be chosen according to some computation modes at the functional level; and expression of how hardware components can be selected via the usage of a library of intellectual properties according to execution performances. The transformation of this model toward synchronous languages is also presented, in order to allow an automatic code generation usable for formal verification, based on techniques such as model checking and controller synthesis, as illustrated in the paper. This work, based on Model-Driven Engineering and the standard UML MARTE profile, has been implemented in Gaspard.

The Effects of Bytecode Generation in XSLT and XQuery

2011 ◽  
Author(s):  
O'Neil Davion Delpratt ◽  
Michael Kay
Keyword(s):  
Open Source ◽  
Code Generation ◽  
Experimental Evaluation ◽  
Query Rewriting ◽  
Relative Importance ◽  
Development Team ◽  
Java Bytecode ◽  
High Level ◽  
Performance Gains

This paper attempts to analyze the performance benefits that are achievable by adding a code generation phase to an XSLT or XQuery engine. This is not done in isolation, but in comparison with the benefits delivered by high-level query rewriting. The two techniques are complementary and independent, but can compete for resources in the development team, so it is useful to understand their relative importance. We use the Saxon XSLT/XQuery processor as a case study, where we can now translate the logic of queries into Java bytecode. We provide an experimental evaluation of the performance of Saxon with the addition of this feature compared to the existing Saxon product. Saxon's Enterprise Edition already delivers a performance benefit over the open source product using the join optimizer and other features. What can we learn from these to achieve further performance gains through direct byte code generation?

Automatic Code Generation and Platform Based Design Methodology: An Engine Management System Design Case Study

2005 ◽  
Author(s):  
Alberto Ferrari ◽  
Giovanni Gaviani ◽  
Giacomo Gentile ◽  
Monti Stefano ◽  
Luigi Romagnoli ◽  
...  
Keyword(s):  
System Design ◽  
Code Generation ◽  
Management System ◽  
Design Methodology ◽  
Engine Management System ◽  
Automatic Code Generation ◽  
Design Case ◽  
Design Case Study ◽  
Automatic Code

scholarly journals Workload Decomposition Strategies for Shared Memory Parallel Systems with OpenMP

2001 ◽  
Vol 9 (2-3) ◽  
pp. 109-122 ◽  
Author(s):  
Beniamino Di Martino ◽  
Sergio Briguglio ◽  
Gregorio Vlad ◽  
Giuliana Fogaccia
Keyword(s):  
Programming Languages ◽  
Parallel Programming ◽  
Shared Memory ◽  
Memory Systems ◽  
Particle In Cell ◽  
Decomposition Strategies ◽  
Programming Effort ◽  
High Level ◽  
Memory Architectures

A crucial issue in parallel programming (both for distributed and shared memory architectures) is work decomposition. Work decomposition task can be accomplished without large programming effort with use of high-level parallel programming languages, such as OpenMP. Anyway particular care must still be payed on achieving performance goals. In this paper we introduce and compare two decomposition strategies, in the framework of shared memory systems, as applied to a case study particle in cell application. A number of different implementations of them, based on the OpenMP language, are discussed with regard to time efficiency, memory occupancy, and program restructuring effort.

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