Ripple Carry Adder Using Two XOR Gates in QCA

2013 ◽  
Vol 467 ◽  
pp. 531-535 ◽  
Author(s):  
Kandula Suresh ◽  
Bahniman Ghosh
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Digital Circuits ◽  
Quantum Dot Cellular Automata ◽  
Ripple Carry Adder ◽  
Number Of Cells

Quantum-dot Cellular Automata (QCA) is a very recent technology which can be used for developing new digital circuits which use very less power [1-2]. This paper mainly aims at using XOR gates to implementation of adder circuit in lesser number of cells and with a higher density.

scholarly journals Design of Nanotechnology Based Hazard Free Digital Circuit using Quantum Dot Cellular Automata

2019 ◽  
Vol 9 (1) ◽  
pp. 1207-1210
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Digital Circuits ◽  
Digital Circuit ◽  
Circuit Analysis ◽  
Basic Component ◽  
Quantum Dot Cellular Automata ◽  
Analysis And Design ◽  
Successful Approach

Currently digital circuits have a high flying role in most communications applications. In this Paper, a successful approach to risk-free circuit analysis and design using quantum dot cellular automata is explored at the Nano level. This paper, which we use for both integrated and continuous digital circuits, is a basic component of QCA circuit operation. The Quantum Dot Cellular Automata Designer Tool is very useful for designing a large risk-free circuit. So the proposed risk-free circuit is designed and simulated using this designing software utensil for three input stages. The proposed framework for the risk-free circuit requires only a small number of major gate operations compared to previous structures because of its three input levels.

scholarly journals Design and Evaluation of Cell Interaction Based Vedic Multiplier Using Quantum-Dot Cellular Automata

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 1036
Author(s):  
Nuriddin Safoev ◽  
Jun-Cheol Jeon
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Communication Networks ◽  
Communication Systems ◽  
High Speed ◽  
Digital Signal ◽  
Cell Interaction ◽  
Quantum Dot Cellular Automata ◽  
Vedic Multiplier ◽  
Ripple Carry Adder

A multiplier is one of the main units for digital signal processing and communication systems. In this paper, a high speed and low complexity multiplier is designed on the basis of quantum-dot cellular automata (QCA), which is considered promising nanotechnology. We focus on Vedic multiplier architectures according to Vedic mathematics from ancient Indian sculptures. In fact, an adder is an important block in the design of almost all types of multipliers and a ripple carry adder is used to design simple multiplier implementations. However, a high-speed multi-bit multiplier requires high-speed adder owing to carry propagation. Cell-interaction-based QCA adders have better improvements over conventional majority-gate-based adders. Therefore, a two-bit Vedic multiplier is proposed in QCA and it is used to implement a four-bit form of the multiplier. The proposed architecture has a lower cell count and area compared to other existing structures. Moreover, simulation results demonstrate that the proposed design is sustainable and can be used to realize complex circuit designs for QCA communication networks.

scholarly journals Implementing Logical Circuits with Four Phase Quantum Dot Cellular Clock using QCA Designer

2020 ◽  
Vol 8 (5) ◽  
pp. 3999-4003
Keyword(s):  
Energy Consumption ◽  
Energy Dissipation ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Lower Energy ◽  
Logical Function ◽  
Quantum Dot Cellular Automata ◽  
Qca Circuits ◽  
Effective Design ◽  
Number Of Cells

Quantum Dot Cellular Automata (QCA) is treated as a most promising technology after CMOS techniques. The major advantages of QCA techniques are faster speed, lower energy consumption and smaller size. The implementation of clocks play very big role in the effective design of QCA circuits. In this paper, a QCA circuit is designed using the concept of QCA clocks. The proposed study describes a new method of implementing the logical function with power depletion analysis. The proposed logical function uses total number of 57 cells in which the area of each cell 372 nm2. The energy dissipation in this implementation is 18.79 meV and the total acquired area is 0.192 µm2. The proposed circuit is implemented utilizing QCA Designer. The proposal is excellent in the realization of nano-scale computing with minimal power utilization. The results are compared with the existing approaches and improvements of 6% in the area required and 7% in the number of cells are achieved

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