Counters Designs with Minimum Number of Cells and Area in the Quantum-Dot Cellular Automata Technology

2019 ◽  
Vol 58 (6) ◽  
pp. 1758-1775 ◽  
Author(s):  
Zaman Amirzadeh ◽  
Mohammad Gholami
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Quantum Dot Cellular Automata ◽  
Minimum Number ◽  
Number Of Cells

Ripple Carry Adder Using Two XOR Gates in QCA

2013 ◽  
Vol 467 ◽  
pp. 531-535 ◽  
Author(s):  
Kandula Suresh ◽  
Bahniman Ghosh
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Digital Circuits ◽  
Quantum Dot Cellular Automata ◽  
Ripple Carry Adder ◽  
Number Of Cells

Quantum-dot Cellular Automata (QCA) is a very recent technology which can be used for developing new digital circuits which use very less power [1-2]. This paper mainly aims at using XOR gates to implementation of adder circuit in lesser number of cells and with a higher density.

scholarly journals Implementing Logical Circuits with Four Phase Quantum Dot Cellular Clock using QCA Designer

2020 ◽  
Vol 8 (5) ◽  
pp. 3999-4003
Keyword(s):  
Energy Consumption ◽  
Energy Dissipation ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Lower Energy ◽  
Logical Function ◽  
Quantum Dot Cellular Automata ◽  
Qca Circuits ◽  
Effective Design ◽  
Number Of Cells

Quantum Dot Cellular Automata (QCA) is treated as a most promising technology after CMOS techniques. The major advantages of QCA techniques are faster speed, lower energy consumption and smaller size. The implementation of clocks play very big role in the effective design of QCA circuits. In this paper, a QCA circuit is designed using the concept of QCA clocks. The proposed study describes a new method of implementing the logical function with power depletion analysis. The proposed logical function uses total number of 57 cells in which the area of each cell 372 nm2. The energy dissipation in this implementation is 18.79 meV and the total acquired area is 0.192 µm2. The proposed circuit is implemented utilizing QCA Designer. The proposal is excellent in the realization of nano-scale computing with minimal power utilization. The results are compared with the existing approaches and improvements of 6% in the area required and 7% in the number of cells are achieved

scholarly journals Efficient circuit design for content-addressable memory in quantum-dot cellular automata technology

2021 ◽  
Vol 3 (10) ◽  
Author(s):  
Mohammad Enayati ◽  
Abdalhossein Rezai ◽  
Asghar Karimi
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Network Routing ◽  
Memory Unit ◽  
Quantum Dot Cellular Automata ◽  
Content Addressable Memory ◽  
Computational Circuits ◽  
Short Time ◽  
Fast Memory ◽  
Number Of Cells

AbstractQuantum-dot cellular automata (QCA) technology is a kind of nanotechnology utilized for building computational circuits. It can be a good technology for overcome CMOS drawbacks at nano-scale due to its low delay and area. The Content-Addressable Memory (CAM) is a very fast memory that can perform search operations in a very short time. This feature makes the relative popularity of these memories and many applications for them, especially in network routing and processors. In this study, a novel loop-based circuit is designed for the QCA memory unit, which reduces area, cell count, latency, and cost. The obtained results using QCADesigner tool version 2.0.3 demonstrate that the designed QCA memory unit utilizes 16 cells, 0.01 µm2 area, and 0.25 clock cycles and has a reduction of 33% in the number of cells, 50% in area, 50% in latency, and 75% in cost compared to existing works. Then, this memory unit is utilized to design an efficient structure for CAM circuit. The results show that the developed structure for CAM circuit has 0.75 clock cycles, 32 cells, and 0.03 µm2 area, and it has a reduction of 20% in the number of cells, 25% in area, 40% in latency, and 75% in cost compared to existing works.

Improved Quantum Dot Cellular Automata 4:1 Multiplexer Circuit Unit

2014 ◽  
Vol 2014 (1) ◽  
pp. 37-44 ◽  
Author(s):  
Arighna Sarkar ◽  
◽  
Debarka Mukhopadhyay ◽  
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Quantum Dot Cellular Automata

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

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