Compressed Sensing Based Neural Signal Processing and Performance Analysis

2014 ◽  
Vol 513-517 ◽  
pp. 1595-1599
Author(s):  
Yu Xi Zhang ◽  
Wen Gui Fan ◽  
Jin Ping Sun
Keyword(s):  
Signal Processing ◽  
Compressed Sensing ◽  
Power Consumption ◽  
Digital Signal ◽  
Data Rate ◽  
Acquisition System ◽  
Signal Acquisition ◽  
Signal Compression ◽  
Sensing Matrix ◽  
Neural Signal

Measurement of neural signal provides important value for study of brain function and the pathogenesis of neurological. With emerging extensive research of electrical activity, more and more neural signal need to be collected, transmitted and stored, making the compression processing of neural signal become important part of digital signal processing. In recent years, ASIC-based wireless neural signal acquisition system has been developed rapidly, encountered strict restrictions on power consumption which is dominant determined by the data rate and complexity of algorithm. In order to reduce power consumption, lower data rate and algorithm with lower complexity needed to be selected when design a neural acquisition system. This paper focus on neural signal compression method based on compressed sensing and its performance and compare it with conventional compression algorithm. We compare complexity of various algorithms in the view of circuit complement, show that the complexity of neural signal compression can be dramatically reduced by using specially designed compressed sensing matrix, thereby reducing the system power consumption.

scholarly journals Development of A Low-Cost Arduino-Based 12-Lead Ecg Acquisition System And Accompanied Labview Application

2019 ◽  
Vol 9 (1) ◽  
pp. 1641-1648
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
Low Cost ◽  
Numerical Data ◽  
Digital Signal ◽  
Acquisition System ◽  
Signal Acquisition ◽  
Frequency Noise ◽  
Ecg Signal ◽  
Active Analog

In this paper, the design of a real-time digital multi--channel ECG signal acquisition system is presented. With the purpose of fabrication towards a simple, compact and low-cost tool for bioelectrical signal processing laboratories, the system is developed to acquire the 12 leads EGC signals and converted to numerical data based on an Arduino module named as Leonardo equipped 12 channels ADC. To observe the EGC waves, the ECG signals are amplified through designed amplifiers with the gain of 60 dB. To reduce the effects from the DC component as well as the baseline wandering and the high frequency noise, the active analog bandpass filter ranged in 0,05 Hz to 100 Hz was designed. The power line noise of 50 Hz also decreased with an active analog bandstop filter with attenuation -38 dB. Under the PC application was built using Labview programing, the low-cost digital ECG signal acquisition system was demonstrated with the requirement of observation in real-time. To clarify the small wave in the digital EGG signal, the limitation of the analog signal processing is improved through the digital filters parameterized in the software to increase the SNR from 1.4 dB to 27.6 dB. Practically, the system is evaluated through a series of experiments on a volunteer person resulting the ECG data is recorded and stored in a TDMS file. Since the system is designed as opened-system, a series of developments towards various applications in biomedical diagnosis based on digital signal analysis techniques is promised to be feasible in the near future.

Signal Acquisition and Processing in Hydraulic Components Test System

2013 ◽  
Vol 846-847 ◽  
pp. 972-976
Author(s):  
Xiao Teng Zeng
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Performance Test ◽  
Performance Testing ◽  
Digital Signal ◽  
Test System ◽  
Processing Method ◽  
Signal Acquisition ◽  
Performance Parameters ◽  
Signal Acquisition And Processing

The key to the performance test system for hydraulic components is to realize real, fast and accurate signal acquisition and processing. By analysis the analog and digital signal processing during hydraulic components Performance testing, a new signal flow scheme is proposed. It described in detail the acquisition and processing method of serial signals and PLC signals, thus solving the lag and distortion during signal processing and realizing the real-time display of data and the automatic report of performance parameters during hydraulic components testing process.

Design of Parametric Loudspeaker and Receiver System

2014 ◽  
Vol 909 ◽  
pp. 222-227
Author(s):  
Zi Yu Chen ◽  
Xin Wei Zhang
Keyword(s):  
Signal Processing ◽  
Digital Signal ◽  
Signal Acquisition ◽  
Median Filtering ◽  
Receiver System ◽  
Audible Sound ◽  
Processing Techniques ◽  
Conventional Systems ◽  
Signal Processing Techniques ◽  
Mean Filtering

Parametric loudspeaker systems have been widely used for projecting highly directional audible sound to a specified area. However, the demodulated signal from parametric loudspeaker suffers from high distortion since the nonlinear interaction among primary waves also generate harmonics. In order to reduce distortion, signal acquisition and digital signal processing techniques can be applied at the receiver. In this paper, a parametric loudspeaker and receiver system is designed to reduce distortion using median filtering and mean filtering at the receiver. Compared to conventional systems, the demodulated signal using proposed techniques exhibits lower distortion.

Flexible Transceiver with Format-Transparent Digital Signal Processing for Ultra-large Data-rate Transmissions

2013 ◽  
Author(s):  
Qunbi Zhuge ◽  
Mohamed Morsy-Osman ◽  
Xian Xu ◽  
Mathieu Chagnon ◽  
Meng Qiu ◽  
...  
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Large Data ◽  
Digital Signal ◽  
Data Rate

scholarly journals Multi-Channel Data Acquisition System Based on FPGA and STM32

2020 ◽  
Vol 38 (2) ◽  
pp. 351-358
Author(s):  
Yue Zhang ◽  
Linwei Tao
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Dynamic Range ◽  
Sampling Rate ◽  
High Capacity ◽  
Acquisition System ◽  
Total Power ◽  
Low Power Consumption ◽  
Signal Acquisition ◽  
And Storage

In order to realize the acquisition and storage of underwater acoustic signals for aiming at the requirements of multi-channel, low power consumption and small volume for underwater receiver extension of sonar system, a multi-channel signal acquisition and storage system based on FPGA and STM32 with variable number of working channels and sampling frequency is designed, in which the system is consisted of 8 pieces, 8 channel and 24 bits high dynamic range Δ-Σ ADS1278 ADC chip to synchronous multi-channel analog signal acquisition. FPGA, as the acquisition sequence and logic control, reads and collates the ADC chip data and writes it into the internal high-capacity FIFO, and adds corresponding operations according to the characteristics of FIFO in an application. SMT32 single-chip microcomputer reads the FIFO data through the high-speed SPI interface with FPGA and writes the multi-channel data into the high-capacity SD card. The testing results have verified that the system has characteristics such as stable and reliable, easy configuration, low power consumption, can guarantee the multichannel data serial transmission, storage, accurate, up to 64 analog signals at the same time the real-time collection and storage, top 20 kHz sampling rate, the system total power of the system of about 3W, data rates up to 100 Mb/s, fully meet the needs of underwater sound acquisition system.

scholarly journals About Possibilities of the Probabilistic Form of Information Representation in Military Computing Devices

2021 ◽  
Vol 19 (4) ◽  
pp. 111-117
Author(s):  
N. E. Sapozhnikov ◽  
V. G. Zolotykh ◽  
A. S. Zakharov
Keyword(s):  
Signal Processing ◽  
Power Consumption ◽  
Digital Signal Processing ◽  
High Speed ◽  
Rapid Development ◽  
Practical Importance ◽  
Digital Signal ◽  
Developed Countries ◽  
Computing Systems ◽  
Complex Problems

At present, digital signal processing involves enormous amounts of computations with large-bit arrays, which are carried out in real time. In connection with the need to solve more and more complex problems, constantly growing requirements are imposed on the main parameters of digital processors (speed, reliability, power consumption, etc.), which determine the computing capabilities of systems with digital signal processing. In turn, the rapid development of microelectronics, its successes make it possible to create more and more high-performance computing systems, which makes it possible to solve more and more complex problems, including in the military sphere. The production of the latest information technology means is a technological task that can be solved exclusively by economically developed countries. Bringing domestic microelectronics to the current world level requires significant investments. Therefore, the study and research of discrete nodes and devices is of the direct practical importance. When developing promising computers, new technological approaches should be applied: minimizing power consumption, maintaining modularity and high computational density within a single node, creating high-speed data transmission with the lowest delays, creating an efficient storage system, and choosing the best types of memory. One of such possible approaches is the use of a non-positional form of information presentation in computing systems for national and military purposes. This gives a number of advantages, the main ones of which are: a decrease (by orders of magnitude) in the hardware volume of computing devices, an increase in the speed of calculations, an increase in the noise immunity of communication channels. To use the above method, it is proposed to include a probabilistic arithmetic device in the information processing device that performs basic arithmetic operations (addition, multiplication, exponentiation, subtraction, division), which are performed without the use of additional algorithms and mechanisms, in contrast to “classical" digital representation of binary information, where all operations are performed on the basis of the addition operation.

scholarly journals Gnss Signal Processing in Gpu

2013 ◽  
Vol 48 (2) ◽  
pp. 51-61 ◽  
Author(s):  
Petr Roule ◽  
Ondřej Jakubov ◽  
Pavel Kovář ◽  
Petr Kařmařík ◽  
František Vejražka
Keyword(s):  
Signal Processing ◽  
Graphics Processing Units ◽  
Digital Signal ◽  
General Purpose ◽  
Global Navigation Satellite Systems ◽  
Acquisition Time ◽  
Signal Acquisition ◽  
Satellite Systems ◽  
Central Processing ◽  
Global Navigation Satellite

ABSTRACT Signal processing of the global navigation satellite systems (GNSS) is a computationally demanding task due to the wide bandwidth of the signals and their complicated modulation schemes. The classical GNSS receivers therefore utilize tailored digital signal processors (DSP) not being flexible in nature. Fortunately, the up-to-date parallel processors or graphical processing units (GPUs) dispose sufficient computational power for processing of not only relatively narrow band GPS L1 C/A signal but also the modernized GPS, GLONASS, Galileo and COMPASS signals. The performance improvement of the modern processors is based on the constantly increasing number of cores. This trend is evident not only from the development of the central processing units (CPUs), but also from the development of GPUs that are nowadays equipped with up to several hundreds of cores optimized for video signals. GPUs include special vector instructions that support implementation of massive parallelism. The new GPUs, named as general-purpose computation on graphics processing units (GPGPU), are able to process both graphic and general data, thus making the GNSS signal processing possible. Application programming interfaces (APIs) supporting GPU parallel processing have been developed and standardized. The most general one, Open Computing Language (Open CL), is now supported by most of the GPU vendors. Next, Compute Unified Device Architecture (CUDA) language was developed for NVidia graphic cards. The CUDA language features optimized signal processing libraries including efficient implementation of the fast Fourier transform (FFT). In this paper, we study the applicability of the GPU approach in GNSS signal acquisition. Two common parallel DSP methods, parallel code space search (PCSS) and double-block zero padding (DBZP), have been investigated. Implementations in the C language for CPU and the CUDA language for GPU are discussed and compared with respect to the acquisition time. It is shown that for signals with long ranging codes (with 10230 number of chips - Galileo E5, GPS L5 etc.). Paper presented at the "European Navigation Conference 2012", held in Gdansk, Poland

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